module modexpng_part_recombinator ( clk, rdy, fsm_state_next, index_last, dsp_x_ce_p, dsp_y_ce_p, ena_x, ena_y, dsp_x_p, dsp_y_p, col_index, col_index_last, slim_bram_xy_addr, fat_bram_xy_bank, fat_bram_xy_addr, fat_bram_x_dout, fat_bram_y_dout, fat_bram_xy_dout_valid ); // // Headers // `include "../rtl/modexpng_mmm_fsm.vh" `include "../rtl/modexpng_parameters.vh" `include "../rtl/modexpng_parameters_x8.vh" input clk; output rdy; input [FSM_STATE_WIDTH-1:0] fsm_state_next; input [7:0] index_last; input dsp_x_ce_p; input dsp_y_ce_p; input ena_x; input ena_y; input [8*47-1:0] dsp_x_p; input [8*47-1:0] dsp_y_p; input [ 4:0] col_index; input [ 4:0] col_index_last; input [ 7:0] slim_bram_xy_addr; output [ 2:0] fat_bram_xy_bank; output [ 7:0] fat_bram_xy_addr; output [ 17:0] fat_bram_x_dout; output [ 17:0] fat_bram_y_dout; output fat_bram_xy_dout_valid; // // Latches // reg [1*47-1:0] dsp_x_p_latch[0:7]; reg [1*47-1:0] dsp_y_p_latch[0:7]; // // Mapping // wire [46:0] dsp_x_p_split[0:7]; wire [46:0] dsp_y_p_split[0:7]; genvar z; generate for (z=0; z 8'd0) begin // rdy_adv <= recomb_msb_cnt_delay_1 == 8'd0; // recomb_msb_dout_delay_0 <= {18{1'bX}}; recomb_msb_dout_delay_1 <= recomb_msb_dout_delay_0; recomb_msb_dout_delay_2 <= recomb_msb_dout_delay_1; // recomb_msb_cnt_delay_0 <= 8'd0; recomb_msb_cnt_delay_1 <= recomb_msb_cnt_delay_0; recomb_msb_cnt_delay_2 <= recomb_msb_cnt_delay_1; // fat_bram_xy_bank_reg <= BANK_FAT_ABH; fat_bram_xy_addr_reg <= recomb_msb_cnt_delay_2; fat_bram_x_dout_reg <= recomb_msb_dout_delay_2; // fat_bram_y_dout_reg <= {18{1'bX}}; fat_bram_xy_dout_valid_reg <= 1'b1; // end else begin // fat_bram_xy_bank_reg <= 3'bXXX; fat_bram_xy_addr_reg <= 8'hXX; fat_bram_x_dout_reg <= {18{1'bX}}; fat_bram_y_dout_reg <= {18{1'bX}}; fat_bram_xy_dout_valid_reg <= 1'b0; // end // end // 2'b01: begin // fat_bram_xy_bank_reg <= BANK_FAT_ABL; fat_bram_xy_addr_reg <= fat_bram_xy_cnt_lsb; fat_bram_x_dout_reg <= {2'b00, recomb_lsb_dout}; // fat_bram_y_dout_reg fat_bram_xy_dout_valid_reg <= 1'b1; // fat_bram_xy_cnt_lsb <= fat_bram_xy_cnt_lsb + 1'b1; // end // 2'b10: begin // if (fat_bram_xy_cnt_msb < 8'd2) begin // recomb_msb_dout_carry_0 <= recomb_msb_dout; recomb_msb_dout_carry_1 <= recomb_msb_dout_carry_0; // fat_bram_xy_bank_reg <= 3'bXXX; fat_bram_xy_addr_reg <= 8'hXX; fat_bram_x_dout_reg <= {18{1'bX}}; // fat_bram_y_dout_reg fat_bram_xy_dout_valid_reg <= 1'b0; // end else begin // fat_bram_xy_bank_reg <= BANK_FAT_ABH; fat_bram_xy_addr_reg <= fat_bram_xy_cnt_msb; fat_bram_x_dout_reg <= {2'b00, recomb_msb_dout}; // fat_bram_y_dout_reg fat_bram_xy_dout_valid_reg <= 1'b1; // end // fat_bram_xy_cnt_msb <= fat_bram_xy_cnt_msb + 1'b1; // end // 2'b11: begin // if (fat_bram_xy_cnt_lsb == index_last) begin // fat_bram_xy_bank_reg <= BANK_FAT_ABL; fat_bram_xy_addr_reg <= fat_bram_xy_cnt_lsb; fat_bram_x_dout_reg <= {2'b00, recomb_lsb_dout}; // fat_bram_y_dout_reg <= {18{1'bX}}; fat_bram_xy_dout_valid_reg <= 1'b1; // fat_bram_xy_cnt_lsb <= 8'd0; // end else begin // fat_bram_xy_bank_reg <= BANK_FAT_ABH; fat_bram_xy_addr_reg <= fat_bram_xy_cnt_lsb; fat_bram_x_dout_reg <= {1'b0, {1'b0, recomb_lsb_dout} + {1'b0, recomb_msb_dout_carry_1}}; // fat_bram_y_dout_reg <= {18{1'bX}}; fat_bram_xy_dout_valid_reg <= 1'b1; // fat_bram_xy_cnt_lsb <= fat_bram_xy_cnt_lsb + 1'b1; // recomb_msb_dout_carry_0 <= {16{1'bX}}; recomb_msb_dout_carry_1 <= recomb_msb_dout_carry_0; // end // recomb_msb_dout_delay_0 <= recomb_msb_dout; recomb_msb_dout_delay_1 <= recomb_msb_dout_delay_0; recomb_msb_dout_delay_2 <= recomb_msb_dout_delay_1; // recomb_msb_cnt_delay_0 <= fat_bram_xy_cnt_msb; recomb_msb_cnt_delay_1 <= recomb_msb_cnt_delay_0; recomb_msb_cnt_delay_2 <= recomb_msb_cnt_delay_1; // fat_bram_xy_cnt_msb <= fat_bram_xy_cnt_msb + 1'b1; // end // endcase // end endmodule