//====================================================================== // // Copyright: 2019, The Commons Conservancy Cryptech Project // SPDX-License-Identifier: BSD-3-Clause // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: // - Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // - Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the distribution. // // - Neither the name of the copyright holder nor the names of its // contributors may be used to endorse or promote products derived from // this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS // IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED // TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A // PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED // TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR // PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF // LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING // NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS // SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // //====================================================================== module modexpng_mmm_dual ( clk, rst_n, ena, rdy, ladder_mode, word_index_last, word_index_last_minus1, force_unity_b, only_reduce, just_multiply, sel_wide_in, sel_narrow_in, rd_wide_xy_ena, rd_wide_xy_ena_aux, rd_wide_xy_bank, rd_wide_xy_bank_aux, rd_wide_xy_addr, rd_wide_xy_addr_aux, rd_wide_x_din, rd_wide_y_din, rd_wide_x_din_aux, rd_wide_y_din_aux, rd_narrow_xy_ena, rd_narrow_xy_bank, rd_narrow_xy_addr, rd_narrow_x_din, rd_narrow_y_din, rcmb_wide_xy_bank, rcmb_wide_xy_addr, rcmb_wide_x_dout, rcmb_wide_y_dout, rcmb_wide_xy_valid, rcmb_narrow_xy_bank, rcmb_narrow_xy_addr, rcmb_narrow_x_dout, rcmb_narrow_y_dout, rcmb_narrow_xy_valid, rcmb_xy_bank, rcmb_xy_addr, rcmb_x_dout, rcmb_y_dout, rcmb_xy_valid, rdct_ena, rdct_rdy ); // // Headers // `include "modexpng_parameters.vh" `include "modexpng_mmm_dual_fsm.vh" // // Ports // input clk; input rst_n; input ena; output rdy; input ladder_mode; input [ OP_ADDR_W -1:0] word_index_last; input [ OP_ADDR_W -1:0] word_index_last_minus1; input force_unity_b; input only_reduce; input just_multiply; input [BANK_ADDR_W -1:0] sel_wide_in; input [BANK_ADDR_W -1:0] sel_narrow_in; output rd_wide_xy_ena; output rd_wide_xy_ena_aux; output [BANK_ADDR_W -1:0] rd_wide_xy_bank; output [BANK_ADDR_W -1:0] rd_wide_xy_bank_aux; output [ OP_ADDR_W * NUM_MULTS_HALF -1:0] rd_wide_xy_addr; output [ OP_ADDR_W -1:0] rd_wide_xy_addr_aux; input [ WORD_EXT_W * NUM_MULTS_HALF -1:0] rd_wide_x_din; input [ WORD_EXT_W * NUM_MULTS_HALF -1:0] rd_wide_y_din; input [ WORD_EXT_W -1:0] rd_wide_x_din_aux; input [ WORD_EXT_W -1:0] rd_wide_y_din_aux; output rd_narrow_xy_ena; output [BANK_ADDR_W -1:0] rd_narrow_xy_bank; output [ OP_ADDR_W -1:0] rd_narrow_xy_addr; input [ WORD_EXT_W -1:0] rd_narrow_x_din; input [ WORD_EXT_W -1:0] rd_narrow_y_din; output [BANK_ADDR_W -1:0] rcmb_wide_xy_bank; output [ OP_ADDR_W -1:0] rcmb_wide_xy_addr; output [ WORD_EXT_W -1:0] rcmb_wide_x_dout; output [ WORD_EXT_W -1:0] rcmb_wide_y_dout; output rcmb_wide_xy_valid; output [BANK_ADDR_W -1:0] rcmb_narrow_xy_bank; output [ OP_ADDR_W -1:0] rcmb_narrow_xy_addr; output [ WORD_EXT_W -1:0] rcmb_narrow_x_dout; output [ WORD_EXT_W -1:0] rcmb_narrow_y_dout; output rcmb_narrow_xy_valid; output [BANK_ADDR_W -1:0] rcmb_xy_bank; output [ OP_ADDR_W -1:0] rcmb_xy_addr; output [ WORD_EXT_W -1:0] rcmb_x_dout; output [ WORD_EXT_W -1:0] rcmb_y_dout; output rcmb_xy_valid; output rdct_ena; input rdct_rdy; // // FSM Declaration // reg [MMM_FSM_STATE_W -1:0] fsm_state = MMM_FSM_STATE_IDLE; reg [MMM_FSM_STATE_W -1:0] fsm_state_next; wire [MMM_FSM_STATE_W -1:0] fsm_state_after_idle; wire [MMM_FSM_STATE_W -1:0] fsm_state_after_mult_square; wire [MMM_FSM_STATE_W -1:0] fsm_state_after_mult_triangle; wire [MMM_FSM_STATE_W -1:0] fsm_state_after_mult_rectangle; wire [MMM_FSM_STATE_W -1:0] fsm_state_after_square_holdoff; // // FSM Process // always @(posedge clk or negedge rst_n) // if (!rst_n) fsm_state <= MMM_FSM_STATE_IDLE; else fsm_state <= fsm_state_next; // // Storage Control Interface // reg wide_xy_ena = 1'b0; reg wide_xy_ena_aux = 1'b0; reg [BANK_ADDR_W -1:0] wide_xy_bank; reg [BANK_ADDR_W -1:0] wide_xy_bank_aux; reg [ OP_ADDR_W -1:0] wide_xy_addr[0:NUM_MULTS_HALF-1]; reg [ OP_ADDR_W -1:0] wide_xy_addr_aux; reg narrow_xy_ena = 1'b0; reg [BANK_ADDR_W -1:0] narrow_xy_bank; reg [ OP_ADDR_W -1:0] narrow_xy_addr; reg [ OP_ADDR_W -1:0] narrow_xy_addr_dly; wire [ OP_ADDR_W -1:0] narrow_xy_addr_inc = narrow_xy_addr + 1'b1; // // Outmap Port Mapping // assign rd_wide_xy_ena = wide_xy_ena; assign rd_wide_xy_ena_aux = wide_xy_ena_aux; assign rd_wide_xy_bank = wide_xy_bank; assign rd_wide_xy_bank_aux = wide_xy_bank_aux; assign rd_wide_xy_addr_aux = wide_xy_addr_aux; assign rd_narrow_xy_ena = narrow_xy_ena; assign rd_narrow_xy_bank = narrow_xy_bank; assign rd_narrow_xy_addr = narrow_xy_addr; genvar z; generate for (z=0; z OP_ADDR_ZERO) wide_xy_addr_next = wide_xy_addr_current - 1'b1; else wide_xy_addr_next = wide_xy_addr_last; endfunction integer j; always @(posedge clk or negedge rst_n) // if (!rst_n) begin wide_xy_ena <= 1'b0; wide_xy_ena_aux <= 1'b0; end else begin // // Wide Address // for (j=0; j