From 584393ac5fc9bbe80887702ec2fc97bee999c5e7 Mon Sep 17 00:00:00 2001 From: "Pavel V. Shatov (Meister)" Date: Mon, 21 Oct 2019 15:13:01 +0300 Subject: Further work: - added core wrapper - fixed module resets across entire core (all the resets are now consistently active-low) - continued refactoring --- rtl/modexpng_core_top.v | 28 +-- rtl/modexpng_dsp_array_block.v | 76 +----- rtl/modexpng_general_worker.v | 20 +- rtl/modexpng_io_block.v | 9 +- rtl/modexpng_io_manager.v | 24 +- rtl/modexpng_mmm_dual.v | 496 +++++++++++++++++++------------------- rtl/modexpng_mmm_dual_fsm.vh | 47 ++++ rtl/modexpng_mmm_fsm.vh | 43 ---- rtl/modexpng_parameters.vh | 2 +- rtl/modexpng_recombinator_block.v | 51 ++-- rtl/modexpng_reductor.v | 29 +-- rtl/modexpng_storage_block.v | 8 +- rtl/modexpng_storage_manager.v | 12 +- rtl/modexpng_uop_engine.v | 18 +- rtl/modexpng_wrapper.v | 393 ++++++++++++++++++++++++++++++ 15 files changed, 787 insertions(+), 469 deletions(-) create mode 100644 rtl/modexpng_mmm_dual_fsm.vh delete mode 100644 rtl/modexpng_mmm_fsm.vh create mode 100644 rtl/modexpng_wrapper.v (limited to 'rtl') diff --git a/rtl/modexpng_core_top.v b/rtl/modexpng_core_top.v index a991c61..18c32bb 100644 --- a/rtl/modexpng_core_top.v +++ b/rtl/modexpng_core_top.v @@ -1,7 +1,7 @@ module modexpng_core_top ( clk, clk_bus, - rst, + rst_n, next, valid, crt_mode, word_index_last_n, @@ -28,7 +28,7 @@ module modexpng_core_top input clk; input clk_bus; - input rst; + input rst_n; input next; output valid; @@ -118,7 +118,7 @@ module modexpng_core_top modexpng_uop_engine uop_engine ( .clk (clk), - .rst (rst), + .rst_n (rst_n), .ena (next), .rdy (valid), @@ -419,7 +419,7 @@ module modexpng_core_top modexpng_storage_block storage_block_x ( .clk (clk), - .rst (rst), + .rst_n (rst_n), .wr_wide_xy_ena (wr_wide_xy_ena_x), .wr_wide_xy_bank (wr_wide_xy_bank_x), @@ -466,7 +466,7 @@ module modexpng_core_top modexpng_storage_block storage_block_y ( .clk (clk), - .rst (rst), + .rst_n (rst_n), .wr_wide_xy_ena (wr_wide_xy_ena_y), .wr_wide_xy_bank (wr_wide_xy_bank_y), @@ -518,7 +518,7 @@ module modexpng_core_top modexpng_storage_manager storage_manager_x ( .clk (clk), - .rst (rst), + .rst_n (rst_n), .wr_wide_xy_ena (wr_wide_xy_ena_x), .wr_wide_xy_bank (wr_wide_xy_bank_x), @@ -584,7 +584,7 @@ module modexpng_core_top modexpng_storage_manager storage_manager_y ( .clk (clk), - .rst (rst), + .rst_n (rst_n), .wr_wide_xy_ena (wr_wide_xy_ena_y), .wr_wide_xy_bank (wr_wide_xy_bank_y), @@ -656,7 +656,7 @@ module modexpng_core_top .clk (clk), .clk_bus (clk_bus), - .rst (rst), + .rst_n (rst_n), .bus_cs (bus_cs), .bus_we (bus_we), @@ -685,7 +685,7 @@ module modexpng_core_top modexpng_io_manager io_manager ( .clk (clk), - .rst (rst), + .rst_n (rst_n), .ena (io_mgr_ena), .rdy (io_mgr_rdy), @@ -755,7 +755,7 @@ module modexpng_core_top modexpng_mmm_dual mmm_x ( .clk (clk), - .rst (rst), + .rst_n (rst_n), .ena (mmm_ena_x), .rdy (mmm_rdy_x), @@ -812,7 +812,7 @@ module modexpng_core_top modexpng_mmm_dual mmm_y ( .clk (clk), - .rst (rst), + .rst_n (rst_n), .ena (mmm_ena_y), .rdy (mmm_rdy_y), @@ -872,7 +872,7 @@ module modexpng_core_top modexpng_reductor reductor_x ( .clk (clk), - .rst (rst), + .rst_n (rst_n), .ena (rdct_ena_x), .rdy (rdct_rdy_x), @@ -909,7 +909,7 @@ module modexpng_core_top modexpng_reductor reductor_y ( .clk (clk), - .rst (rst), + .rst_n (rst_n), .ena (rdct_ena_y), .rdy (rdct_rdy_y), @@ -950,7 +950,7 @@ module modexpng_core_top modexpng_general_worker general_worker ( .clk (clk), - .rst (rst), + .rst_n (rst_n), .ena (wrk_ena), .rdy (wrk_rdy), diff --git a/rtl/modexpng_dsp_array_block.v b/rtl/modexpng_dsp_array_block.v index 6b4ad3c..1444aa7 100644 --- a/rtl/modexpng_dsp_array_block.v +++ b/rtl/modexpng_dsp_array_block.v @@ -38,81 +38,7 @@ module modexpng_dsp_array_block ce_a1 <= ce_a0; ce_a2 <= ce_a1; ce_b1 <= ce_b0; - end - - /// - wire [46:0] p_debug_direct; - wire [17:0] casc_a_debug_direct; - wire [15:0] casc_b_debug_direct; - - wire [46:0] p_debug_cascade; - - wire [46:0] p_ref_direct = p[ 0 +: MAC_W]; - wire [46:0] p_ref_cascade = p[MAC_W +: MAC_W]; - - modexpng_dsp_slice_wrapper_xilinx # - ( - .AB_INPUT("DIRECT"), - .B_REG(2) - ) - dsp_debug_direct - ( - .clk (clk), - - .ce_a1 (ce_a0), - .ce_b1 (ce_b0), - .ce_a2 (ce_a1), - .ce_b2 (ce_b1), - .ce_m (ce_m), - .ce_p (ce_p), - .ce_mode (ce_mode), - - .a (a[0 +: 18]), - .b (b), - .p (p_debug_direct), - - .inmode ({DSP48E1_INMODE_W{1'b0}}), - .opmode ({1'b0, mode_z[0], 1'b0, 2'b01, 2'b01}), - .alumode ({DSP48E1_ALUMODE_W{1'b0}}), - - .casc_a_in (WORD_EXT_ZERO), - .casc_b_in (WORD_ZERO), - - .casc_a_out (casc_a_debug_direct), - .casc_b_out (casc_b_debug_direct) - ); - - modexpng_dsp_slice_wrapper_xilinx # - ( - .AB_INPUT("CASCADE"), - .B_REG(1) - ) - dsp_debug_cascade - ( - .clk (clk), - - .ce_a1 (ce_a1), - .ce_b1 (1'b0), - .ce_a2 (ce_a2), - .ce_b2 (ce_b1), - .ce_m (ce_m), - .ce_p (ce_p), - .ce_mode (ce_mode), - - .a (a[0 +: 18]), - .b (b), - .p (p_debug_cascade), - - .inmode ({DSP48E1_INMODE_W{1'b0}}), - .opmode ({1'b0, mode_z[1], 1'b0, 2'b01, 2'b01}), - .alumode ({DSP48E1_ALUMODE_W{1'b0}}), - - .casc_a_in (casc_a_debug_direct), - .casc_b_in (casc_b_debug_direct), - - .casc_a_out (), - .casc_b_out () - ); + end genvar z; generate for (z=0; z MAX_OP_W) fix_modulus_bits = MAX_OP_W[BIT_INDEX_W:ZEROES_BIT_INDEX_W]; + else fix_modulus_bits = width [BIT_INDEX_W:ZEROES_BIT_INDEX_W]; + endfunction + + function [OP_ADDR_W-1: 0] calc_modulus_num_words_n; + input [BIT_INDEX_W:ZEROES_BIT_INDEX_W] width; + calc_modulus_num_words_n = {width, {(ZEROES_BIT_INDEX_W-WORD_MUX_W){1'b0}}} - 1'b1; // truncates msb + endfunction + + function [OP_ADDR_W-1: 0] calc_modulus_num_words_pq; + input [BIT_INDEX_W:ZEROES_BIT_INDEX_W] width; + calc_modulus_num_words_pq = {width, {(ZEROES_BIT_INDEX_W-WORD_MUX_W-1){1'b0}}} - 1'b1; // fits exactly + endfunction + + task write_modulus_bits; + input [BIT_INDEX_W:0] width; + begin + wrap_modulus_bits_msb <= fix_modulus_bits(width); + wrap_word_index_last_n <= calc_modulus_num_words_n(fix_modulus_bits(width)); + wrap_word_index_last_pq <= calc_modulus_num_words_pq(fix_modulus_bits(width)); + end + endtask + + + // + // Update exponent width + // + function [BIT_INDEX_W:0] fix_exponent_bits; + input [BIT_INDEX_W:0] width; + if (width < MIN_EXP_W) fix_exponent_bits = MIN_EXP_W; + else if (width > MAX_OP_W ) fix_exponent_bits = MAX_OP_W; + else fix_exponent_bits = width; + endfunction + + function [BIT_INDEX_W-1:0] calc_exponent_num_bits_n; + input [BIT_INDEX_W :0] width; + calc_exponent_num_bits_n = width - 1'b1; // truncates msb + endfunction + + function [BIT_INDEX_W-1:0] calc_exponent_num_bits_pq; + input [BIT_INDEX_W: 0] width; + calc_exponent_num_bits_pq = width[BIT_INDEX_W:1] - 1'b1; // fits exactly + endfunction + + task write_exponent_bits; + input [BIT_INDEX_W:0] width; + begin + wrap_exponent_bits <= fix_exponent_bits(width); + wrap_bit_index_last_n <= calc_exponent_num_bits_n(fix_exponent_bits(width)); + wrap_bit_index_last_pq <= calc_exponent_num_bits_pq(fix_exponent_bits(width)); + end + endtask + + + // + // Read Interface + // + always @(posedge clk) + // + if (cs && addr_msb_is_wrap) + // + case (address) + // + ADDR_NAME0: wrap_read_data <= CORE_NAME0; + ADDR_NAME1: wrap_read_data <= CORE_NAME1; + ADDR_VERSION: wrap_read_data <= CORE_VERSION; + ADDR_CONTROL: wrap_read_data <= {{30{1'b0}}, wrap_reg_control, 1'b0}; + ADDR_STATUS: wrap_read_data <= {{30{1'b0}}, wrap_reg_status, 1'b1}; + // + ADDR_MODE: wrap_read_data <= {{30{1'b0}}, wrap_reg_mode, 1'b0}; + ADDR_MODULUS_BITS: wrap_read_data <= {{(31-BIT_INDEX_W){1'b0}}, wrap_modulus_bits_msb, {ZEROES_BIT_INDEX_W{1'b0}}}; + ADDR_EXPONENT_BITS: wrap_read_data <= {{(31-BIT_INDEX_W){1'b0}}, wrap_exponent_bits}; + ADDR_BANK_BITS: wrap_read_data <= MAX_OP_W; + ADDR_NUM_MULTS: wrap_read_data <= NUM_MULTS; + // + default: wrap_read_data <= 32'h00000000; + // + endcase + + + // + // Register / Core Memory Selector + // + reg [1:0] addr_msb_last; + + wire addr_msb_last_is_wrap = addr_msb_last == ADDR_MSB_WRAP; + + always @(posedge clk) + addr_msb_last <= addr_msb; + + assign read_data = addr_msb_last_is_wrap ? wrap_read_data : core_read_data; + + +endmodule -- cgit v1.2.3