From affada8d5da7426d22035360c3674ab3b3311ab5 Mon Sep 17 00:00:00 2001 From: "Pavel V. Shatov (Meister)" Date: Thu, 3 Oct 2019 16:40:25 +0300 Subject: Reworked storage architecture (moved I/O memory to a separate module, since there's only one instance of input/output values, while storage manager has dual storage space for P and Q multipliers). Started working on microcoded layer, added input operation and modular multiplication. --- rtl/modexpng_sdp_36k_x18_wrapper.v | 67 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 67 insertions(+) create mode 100644 rtl/modexpng_sdp_36k_x18_wrapper.v (limited to 'rtl/modexpng_sdp_36k_x18_wrapper.v') diff --git a/rtl/modexpng_sdp_36k_x18_wrapper.v b/rtl/modexpng_sdp_36k_x18_wrapper.v new file mode 100644 index 0000000..ded9425 --- /dev/null +++ b/rtl/modexpng_sdp_36k_x18_wrapper.v @@ -0,0 +1,67 @@ +module modexpng_sdp_36k_x18_wrapper +( + clk, + + ena, wea, + addra, dina, + + enb, regceb, + addrb, doutb +); + + + // + // Headers + // + `include "modexpng_parameters.vh" + + + // + // Ports + // + input clk; + + input ena; + input wea; + input [BANK_ADDR_W + OP_ADDR_W -1:0] addra; + input [ WORD_EXT_W -1:0] dina; + + input enb; + input regceb; + input [BANK_ADDR_W + OP_ADDR_W -1:0] addrb; + output [ WORD_EXT_W -1:0] doutb; + + // + // Memory + // + reg [WORD_EXT_W -1:0] mem[0:2**(BANK_ADDR_W+OP_ADDR_W)-1]; + + // + // Write Port + // + always @(posedge clk) + // + if (ena && wea) + mem[addra] <= dina; + + // + // Read Port + // + reg [WORD_EXT_W -1:0] doutb_reg1; + reg [WORD_EXT_W -1:0] doutb_reg2; + + assign doutb = doutb_reg2; + + always @(posedge clk) + // + if (enb) + doutb_reg1 <= mem[addrb]; + + always @(posedge clk) + // + if (regceb) + doutb_reg2 <= doutb_reg1; + + + +endmodule -- cgit v1.2.3