From 71f70252dfc7e41103dde420a721be8aa48486d5 Mon Sep 17 00:00:00 2001
From: "Pavel V. Shatov (Meister)" <meisterpaul1@yandex.ru>
Date: Tue, 1 Oct 2019 16:18:33 +0300
Subject: Redesigned core architecture, unified bank structure. All storage
 blocks now have eight 4kbit entries and occupy one 36K BRAM tile.

---
 rtl/modexpng_sdp_36k_wrapper.v | 72 ++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 72 insertions(+)
 create mode 100644 rtl/modexpng_sdp_36k_wrapper.v

(limited to 'rtl/modexpng_sdp_36k_wrapper.v')

diff --git a/rtl/modexpng_sdp_36k_wrapper.v b/rtl/modexpng_sdp_36k_wrapper.v
new file mode 100644
index 0000000..0295697
--- /dev/null
+++ b/rtl/modexpng_sdp_36k_wrapper.v
@@ -0,0 +1,72 @@
+module modexpng_sdp_36k_wrapper
+(
+    clk,
+    
+    ena, wea,
+    addra, dina,
+    
+    enb, regceb,
+    addrb, doutb
+);
+
+
+    //
+    // Headers
+    //
+    `include "../rtl/modexpng_parameters.vh"
+
+
+    //
+    // Ports
+    //
+    input                                 clk;
+    
+    input                                 ena;
+    input                                 wea;
+    input  [BANK_ADDR_W + OP_ADDR_W -1:0] addra;
+    input  [             WORD_EXT_W -1:0] dina;
+    
+    input                                 enb;
+    input                                 regceb;
+    input  [BANK_ADDR_W + OP_ADDR_W -1:0] addrb;
+    output [             WORD_EXT_W -1:0] doutb;
+
+    //
+    // BRAM_SDP_MACRO
+    //
+    BRAM_SDP_MACRO #
+    (
+        .DEVICE                 ("7SERIES"),
+        
+        .BRAM_SIZE              ("36Kb"),
+        
+        .WRITE_WIDTH            (WORD_EXT_W),
+        .READ_WIDTH             (WORD_EXT_W),
+        
+        .DO_REG                 (1),
+        .WRITE_MODE             ("READ_FIRST"),
+        
+        .SRVAL                  (72'h000000000000000000),
+        .INIT                   (72'h000000000000000000),
+
+        .INIT_FILE              ("NONE"),
+        .SIM_COLLISION_CHECK    ("NONE")
+    )
+    BRAM_SDP_MACRO_inst
+    (
+        .RST        (1'b0),
+    
+        .WRCLK      (clk),
+        .WREN       (ena),
+        .WE         ({2{wea}}),
+        .WRADDR     (addra),
+        .DI         (dina),
+        
+        .RDCLK      (clk),
+        .RDEN       (enb),
+        .REGCE      (regceb),
+        .RDADDR     (addrb),
+        .DO         (doutb)
+    );
+    
+endmodule
-- 
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