From 72902f5b40ac695786f5103d2a5a456c6c7ee83f Mon Sep 17 00:00:00 2001 From: "Pavel V. Shatov (Meister)" Date: Mon, 21 Oct 2019 13:04:07 +0300 Subject: Redesigned the testbench. Core clock does not necessarily need to be twice faster than the bus clock now. It can be the same, or say four times faster. --- rtl/modexpng_dsp_slice_primitive.vh | 9 +++++++++ 1 file changed, 9 insertions(+) create mode 100644 rtl/modexpng_dsp_slice_primitive.vh (limited to 'rtl/modexpng_dsp_slice_primitive.vh') diff --git a/rtl/modexpng_dsp_slice_primitive.vh b/rtl/modexpng_dsp_slice_primitive.vh new file mode 100644 index 0000000..02d9a5d --- /dev/null +++ b/rtl/modexpng_dsp_slice_primitive.vh @@ -0,0 +1,9 @@ +`ifndef MODEXPNG_ENABLE_DEBUG + +`define MODEXPNG_DSP_SLICE modexpng_dsp_slice_wrapper_xilinx + +`else + +`define MODEXPNG_DSP_SLICE modexpng_dsp_slice_wrapper_generic + +`endif -- cgit v1.2.3