From c5d210149af3e40170fcd01047d3b844ed65871c Mon Sep 17 00:00:00 2001
From: "Pavel V. Shatov (Meister)" <meisterpaul1@yandex.ru>
Date: Mon, 3 Feb 2020 22:38:38 +0300
Subject: Updated DSP slice wrappers for the new partial product recombination
 algorithm:  - unified clock enable for A:B and C ports  - A:B and C ports now
 always have fixed 1-cycle latency  - added new Z multiplexor modes in the
 generic wrapper

---
 rtl/modexpng_dsp_slice_addsub_wrapper_xilinx.v | 31 ++++++++++----------------
 1 file changed, 12 insertions(+), 19 deletions(-)

(limited to 'rtl/modexpng_dsp_slice_addsub_wrapper_xilinx.v')

diff --git a/rtl/modexpng_dsp_slice_addsub_wrapper_xilinx.v b/rtl/modexpng_dsp_slice_addsub_wrapper_xilinx.v
index b8dcbce..2af6481 100644
--- a/rtl/modexpng_dsp_slice_addsub_wrapper_xilinx.v
+++ b/rtl/modexpng_dsp_slice_addsub_wrapper_xilinx.v
@@ -30,15 +30,10 @@
 //
 //======================================================================
 
-module modexpng_dsp_slice_addsub_wrapper_xilinx #
-(
-    AB_REG = 1
-)
+module modexpng_dsp_slice_addsub_wrapper_xilinx
 (
     clk,
-    ce_ab1,
-    ce_ab2,
-    ce_c,
+    ce_abc,
     ce_p,
     ce_ctrl,
     ab, c, p,
@@ -53,9 +48,7 @@ module modexpng_dsp_slice_addsub_wrapper_xilinx #
     `include "modexpng_dsp48e1.vh"
         
     input                              clk;
-    input                              ce_ab1;
-    input                              ce_ab2;
-    input                              ce_c;
+    input                              ce_abc;
     input                              ce_p;
     input                              ce_ctrl;
     input  [         DSP48E1_C_W -1:0] ab;
@@ -81,15 +74,15 @@ module modexpng_dsp_slice_addsub_wrapper_xilinx #
 
     DSP48E1 #
     (
-        .AREG                   (AB_REG),
-        .BREG                   (AB_REG),
+        .AREG                   (1),
+        .BREG                   (1),
         .CREG                   (1),
         .DREG                   (0),
         .ADREG                  (0),
         .MREG                   (0),
         .PREG                   (1),
-        .ACASCREG               (AB_REG),
-        .BCASCREG               (AB_REG),
+        .ACASCREG               (1),
+        .BCASCREG               (1),
         .INMODEREG              (0),
         .OPMODEREG              (1),
         .ALUMODEREG             (1),
@@ -115,12 +108,12 @@ module modexpng_dsp_slice_addsub_wrapper_xilinx #
     (
         .CLK                (clk),
     
-        .CEA1               (ce_ab1),
-        .CEB1               (ce_ab1),
-        .CEA2               (ce_ab2),
-        .CEB2               (ce_ab2),
+        .CEA1               (1'b0),
+        .CEB1               (1'b0),
+        .CEA2               (ce_abc),
+        .CEB2               (ce_abc),
         .CEAD               (1'b0),
-        .CEC                (ce_c),
+        .CEC                (ce_abc),
         .CED                (1'b0),
         .CEM                (1'b0),
         .CEP                (ce_p),
-- 
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