From 71f70252dfc7e41103dde420a721be8aa48486d5 Mon Sep 17 00:00:00 2001
From: "Pavel V. Shatov (Meister)" <meisterpaul1@yandex.ru>
Date: Tue, 1 Oct 2019 16:18:33 +0300
Subject: Redesigned core architecture, unified bank structure. All storage
 blocks now have eight 4kbit entries and occupy one 36K BRAM tile.

---
 rtl/modexpng_dsp_array_block.v | 72 +++++++++++++++++++++++-------------------
 1 file changed, 39 insertions(+), 33 deletions(-)

(limited to 'rtl/modexpng_dsp_array_block.v')

diff --git a/rtl/modexpng_dsp_array_block.v b/rtl/modexpng_dsp_array_block.v
index 9c4ee93..8ab64f0 100644
--- a/rtl/modexpng_dsp_array_block.v
+++ b/rtl/modexpng_dsp_array_block.v
@@ -1,24 +1,30 @@
 module modexpng_dsp_array_block
 (
-    input             clk,
-    
-    input             ce_a,
-    input             ce_b,
-    input             ce_m,
-    input             ce_p,
-    input             ce_mode,
+    clk,
+    ce_a, ce_b, ce_m, ce_p, ce_mode,
+    mode_z,
+    a, b, p
+);
+
+    `include "modexpng_dsp48e1.vh"
+    `include "modexpng_parameters.vh"
 
-    input  [9   -1:0] mode_z,
+    input                                            clk;
     
-    input  [5*18-1:0] a,
-    input  [1*16-1:0] b,
-    output [9*47-1:0] p
-);
+    input                                            ce_a;
+    input                                            ce_b;
+    input                                            ce_m;
+    input                                            ce_p;
+    input                                            ce_mode;
 
-    `include "modexpng_parameters_x8.vh"
+    input  [                     NUM_MULTS_AUX -1:0] mode_z;
+    
+    input  [NUM_MULTS_HALF_AUX * WORD_EXT_W    -1:0] a;
+    input  [                     WORD_W        -1:0] b;
+    output [NUM_MULTS_AUX      * MAC_W         -1:0] p;
     
-    wire [17:0] casc_a[0:3];
-    wire [15:0] casc_b[0:3];
+    wire [WORD_EXT_W -1:0] casc_a[0:NUM_MULTS_HALF-1];
+    wire [    WORD_W -1:0] casc_b[0:NUM_MULTS_HALF-1];
     
     wire ce_a0 = ce_a;
     reg  ce_a1 = 1'b0;
@@ -35,7 +41,7 @@ module modexpng_dsp_array_block
         
     
     genvar z;
-    generate for (z=0; z<(NUM_MULTS/2); z=z+1)
+    generate for (z=0; z<NUM_MULTS_HALF; z=z+1)
         //
         begin : gen_DSP48E1
             //        
@@ -56,16 +62,16 @@ module modexpng_dsp_array_block
                 .ce_p           (ce_p),
                 .ce_mode        (ce_mode),
                 
-                .a              (a[z*18+:18]),
+                .a              (a[z*WORD_EXT_W +: WORD_EXT_W]),
                 .b              (b),
-                .p              (p[47*2*z+:47]),
+                .p              (p[(2*z)*MAC_W +: MAC_W]),
                 
-                .inmode         (5'b00000),
+                .inmode         ({DSP48E1_INMODE_W{1'b0}}),
                 .opmode         ({1'b0, mode_z[2*z], 1'b0, 2'b01, 2'b01}),
-                .alumode        (4'b0000),
+                .alumode        ({DSP48E1_ALUMODE_W{1'b0}}),
                 
-                .casc_a_in      ({18{1'b0}}),
-                .casc_b_in      ({16{1'b0}}),
+                .casc_a_in      (WORD_EXT_NULL),
+                .casc_b_in      (WORD_NULL),
                 
                 .casc_a_out     (casc_a[z]),
                 .casc_b_out     (casc_b[z])
@@ -88,13 +94,13 @@ module modexpng_dsp_array_block
                 .ce_p           (ce_p),
                 .ce_mode        (ce_mode),
                 
-                .a              (a[z*18+:18]),
+                .a              (a[z*WORD_EXT_W +: WORD_EXT_W]),
                 .b              (b),
-                .p              (p[47*(2*z+1)+:47]),
+                .p              (p[(2*z+1)*MAC_W +: MAC_W]),
                 
-                .inmode         (5'b00000),
+                .inmode         ({DSP48E1_INMODE_W{1'b0}}),
                 .opmode         ({1'b0, mode_z[2*z+1], 1'b0, 2'b01, 2'b01}),
-                .alumode        (4'b0000),
+                .alumode        ({DSP48E1_ALUMODE_W{1'b0}}),
                 
                 .casc_a_in      (casc_a[z]),
                 .casc_b_in      (casc_b[z]),
@@ -124,16 +130,16 @@ module modexpng_dsp_array_block
         .ce_p           (ce_p),
         .ce_mode        (ce_mode),
         
-        .a              (a[4*18+:18]),
+        .a              (a[NUM_MULTS_HALF*WORD_EXT_W +: WORD_EXT_W]),
         .b              (b),
-        .p              (p[47*2*4+:47]),
+        .p              (p[(2*NUM_MULTS_HALF)*MAC_W +: MAC_W]),
         
-        .inmode         (5'b00000),
-        .opmode         ({1'b0, mode_z[2*4], 1'b0, 2'b01, 2'b01}),
-        .alumode        (4'b0000),
+        .inmode         ({DSP48E1_INMODE_W{1'b0}}),
+        .opmode         ({1'b0, mode_z[2*NUM_MULTS_HALF], 1'b0, 2'b01, 2'b01}),
+        .alumode        ({DSP48E1_ALUMODE_W{1'b0}}),
         
-        .casc_a_in      ({18{1'b0}}),
-        .casc_b_in      ({16{1'b0}}),
+        .casc_a_in      (WORD_EXT_NULL),
+        .casc_b_in      (WORD_NULL),
         
         .casc_a_out     (),
         .casc_b_out     ()
-- 
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