From 72902f5b40ac695786f5103d2a5a456c6c7ee83f Mon Sep 17 00:00:00 2001 From: "Pavel V. Shatov (Meister)" Date: Mon, 21 Oct 2019 13:04:07 +0300 Subject: Redesigned the testbench. Core clock does not necessarily need to be twice faster than the bus clock now. It can be the same, or say four times faster. --- rtl/modexpng_dsp48e1.vh | 1 + 1 file changed, 1 insertion(+) (limited to 'rtl/modexpng_dsp48e1.vh') diff --git a/rtl/modexpng_dsp48e1.vh b/rtl/modexpng_dsp48e1.vh index bc3d55c..410ad41 100644 --- a/rtl/modexpng_dsp48e1.vh +++ b/rtl/modexpng_dsp48e1.vh @@ -6,3 +6,4 @@ localparam DSP48E1_P_W = 48; localparam DSP48E1_INMODE_W = 5; localparam DSP48E1_OPMODE_W = 7; localparam DSP48E1_ALUMODE_W = 4; + -- cgit v1.2.3