Age | Commit message (Collapse) | Author |
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Changed all copyrights from Nordunet to Commons Conservancy, since they've
been the copyright holder since the end of 2018.
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* take advantage of the cascade paths between DSP slices
* decrease latency of operation
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the subtle math overflow bug introduced while switching to DSP-based partial
multiplication product recombination.
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wrapper names.
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Moved micro-operations handler into a separate module file, this way we don't
have any synthesized stuff in the top-level module, just instantiations. This
is more consistent from the design partitioning point of view. Btw, Xilinx
claims their tools work better that way too, but who knows...
Added optional simulation-only code to assist debugging. Un-comment the
ENABLE_DEBUG `define in 'rtl/modexpng_parameters.vh' to use, but don't ever
try to synthesize the core with debugging enabled.
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have eight 4kbit entries and occupy one 36K BRAM tile.
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