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Changed all copyrights from Nordunet to Commons Conservancy, since they've
been the copyright holder since the end of 2018.
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* flush console after each ladder iteration for smoother progress output
* ability to truncate internal powering ladder loop at desired step (this will
only work when using simulation mode, obviously)
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necessary changes to make it work after the general worker update. Also moved
debug simulation-time code into a separate file.
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- added core wrapper
- fixed module resets across entire core (all the resets are now consistently
active-low)
- continued refactoring
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Moved micro-operations handler into a separate module file, this way we don't
have any synthesized stuff in the top-level module, just instantiations. This
is more consistent from the design partitioning point of view. Btw, Xilinx
claims their tools work better that way too, but who knows...
Added optional simulation-only code to assist debugging. Un-comment the
ENABLE_DEBUG `define in 'rtl/modexpng_parameters.vh' to use, but don't ever
try to synthesize the core with debugging enabled.
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is basically
a block memory data mover, but it can also do some supporting operations required for the
Garner's formula part of the exponentiation.
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there's
only one instance of input/output values, while storage manager has dual storage space
for P and Q multipliers).
Started working on microcoded layer, added input operation and modular multiplication.
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