Age | Commit message (Collapse) | Author | |
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2019-10-21 | Redesigned the testbench. Core clock does not necessarily need to be twice | Pavel V. Shatov (Meister) | |
faster than the bus clock now. It can be the same, or say four times faster. |
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index : core/math/modexpng | |
"Next-generation" modular exponentiation using specialized DSP slices present in Artix-7 FPGA | git repositories |
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Age | Commit message (Collapse) | Author | |
---|---|---|---|
2019-10-21 | Redesigned the testbench. Core clock does not necessarily need to be twice | Pavel V. Shatov (Meister) | |
faster than the bus clock now. It can be the same, or say four times faster. |