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AgeCommit message (Collapse)Author
2020-01-20For the new general worker module to work we need dynamic switching of DSPPavel V. Shatov (Meister)
OPMODE, ALUMODE and CARRYINSEL ports, thus more defined constants.
2019-10-23Added missing copyright headers.Pavel V. Shatov (Meister)
2019-10-21Redesigned the testbench. Core clock does not necessarily need to be twicePavel V. Shatov (Meister)
faster than the bus clock now. It can be the same, or say four times faster.
2019-10-01Redesigned core architecture, unified bank structure. All storage blocks nowPavel V. Shatov (Meister)
have eight 4kbit entries and occupy one 36K BRAM tile.