| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2019-10-21 | Redesigned the testbench. Core clock does not necessarily need to be twice | Pavel V. Shatov (Meister) | |
| faster than the bus clock now. It can be the same, or say four times faster. | |||
| 2019-10-01 | Redesigned core architecture, unified bank structure. All storage blocks now | Pavel V. Shatov (Meister) | |
| have eight 4kbit entries and occupy one 36K BRAM tile. | |||
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index : core/math/modexpng | |
| "Next-generation" modular exponentiation using specialized DSP slices present in Artix-7 FPGA | git repositories |
| aboutsummaryrefslogtreecommitdiff |