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- added core wrapper
- fixed module resets across entire core (all the resets are now consistently
active-low)
- continued refactoring
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faster than the bus clock now. It can be the same, or say four times faster.
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Moved micro-operations handler into a separate module file, this way we don't
have any synthesized stuff in the top-level module, just instantiations. This
is more consistent from the design partitioning point of view. Btw, Xilinx
claims their tools work better that way too, but who knows...
Added optional simulation-only code to assist debugging. Un-comment the
ENABLE_DEBUG `define in 'rtl/modexpng_parameters.vh' to use, but don't ever
try to synthesize the core with debugging enabled.
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Added modular subtraction micro-operation
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addition of AB and M then reduction by right-shift.
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"rectangular" stage of the multiplication process, i.e. computation of how many
copies of the modulus N to add to the intermediate product AB to zeroize the
lower half: M = Q * N.
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part of multiplication, i.e. compute the "magic" reduction coefficient
Q = LSB(AB) * N_COEFF.
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do the "square" part of the multiplication, i.e. compute the twice larger
intermediate product AB = A * B.
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