| Age | Commit message (Expand) | Author |
|---|
| 2020-01-21 | Added more meaningful constants to avoid certain hardcoded numbers. | Pavel V. Shatov (Meister) |
| 2020-01-21 | Tiny cosmetic typo fix ("dst" -> "dsp") | Pavel V. Shatov (Meister) |
| 2020-01-20 | For the new general worker module to work we need dynamic switching of DSP | Pavel V. Shatov (Meister) |
| 2020-01-20 | Updated uOP engine to match the changes made to the general worker module | Pavel V. Shatov (Meister) |
| 2020-01-20 | Updated microcode source to match the changes made to general worker module. | Pavel V. Shatov (Meister) |
| 2020-01-20 | Cosmetic fix that only involves debug output during simulation. | Pavel V. Shatov (Meister) |
| 2020-01-20 | Added two pairs of new wrappers. | Pavel V. Shatov (Meister) |
| 2020-01-20 | Removed old DSP wrappers. | Pavel V. Shatov (Meister) |
| 2020-01-20 | * DSP slices now have two use modes: MULT and ADD/SUB | Pavel V. Shatov (Meister) |
| 2020-01-16 | This commit modifies the REGULAR_ADD_UNEVEN micro-operation to use DSP slices | Pavel V. Shatov (Meister) |
| 2020-01-16 | Reworked modular subtraction micro-operation. Previously it used "two-pass" | Pavel V. Shatov (Meister) |
| 2020-01-16 | Turns out, fabric addition and subtraction in the general worker module are | Pavel V. Shatov (Meister) |
| 2020-01-16 | Had to rework the general worker module to reach 180 MHz core clock. The module | Pavel V. Shatov (Meister) |
| 2019-11-26 | One more cosmetic fix. | Pavel V. Shatov (Meister) |
| 2019-11-26 | Cosmetic fix. | Pavel V. Shatov (Meister) |
| 2019-11-26 | Forgot to push minor cosmetic fix. | Pavel V. Shatov (Meister) |
| 2019-11-20 | Small change to the reductor module to try to get past 180 MHz. Previously BRAM | Pavel V. Shatov (Meister) |
| 2019-11-19 | Removed the latch accidentally created while pipelining the uOP engine module. | Pavel V. Shatov (Meister) |
| 2019-11-18 | Refactored reductor module. | Pavel V. Shatov (Meister) |
| 2019-11-16 | The uOP engine didn't compile at 180 MHz. The pipeline had two stages: FETCH | Pavel V. Shatov (Meister) |
| 2019-11-13 | Beautified the README.md, should look somewhat less nasty now. | Pavel V. Shatov (Meister) |
| 2019-10-23 | Added missing copyright headers. | Pavel V. Shatov (Meister) |
| 2019-10-23 | Added demo driver code for STM32. | Pavel V. Shatov (Meister) |
| 2019-10-23 | Added readme file. | Pavel V. Shatov (Meister) |
| 2019-10-23 | Fixed port width mismatch warning. | Pavel V. Shatov (Meister) |
| 2019-10-23 | Added simulation-only code to measure multiplier load. | Pavel V. Shatov (Meister) |
| 2019-10-23 | Fixed all the testbenches to work with the latest RTL sources. | Pavel V. Shatov (Meister) |
| 2019-10-21 | Reworked testbench, clk_sys and clk_core can now have any ratio, not | Pavel V. Shatov (Meister) |
| 2019-10-21 | Further work: | Pavel V. Shatov (Meister) |
| 2019-10-21 | Added support for non-CRT mode. Further refactoring. | Pavel V. Shatov (Meister) |
| 2019-10-21 | Redesigned the testbench. Core clock does not necessarily need to be twice | Pavel V. Shatov (Meister) |
| 2019-10-21 | Entire CRT signature algorithm works by now. | Pavel V. Shatov (Meister) |
| 2019-10-21 | Added the regular (not modular) addition operation required during the final | Pavel V. Shatov (Meister) |
| 2019-10-21 | Added "MERGE_LH" micro-operation. To be able to do Garner's formula we need | Pavel V. Shatov (Meister) |
| 2019-10-21 | Refactored general worker module | Pavel V. Shatov (Meister) |
| 2019-10-03 | Added more micro-operations, entire Montgomery exponentiation ladder works now. | Pavel V. Shatov (Meister) |
| 2019-10-03 | Added more micro-operations, also added "general worker" module. The worker i... | Pavel V. Shatov (Meister) |
| 2019-10-03 | Expanded micro-operation parameters (added dedicated control bit to force the... | Pavel V. Shatov (Meister) |
| 2019-10-03 | Reworked storage architecture (moved I/O memory to a separate module, since t... | Pavel V. Shatov (Meister) |
| 2019-10-03 | Redesigned storage modules, added top-level module, added I/O storage space. | Pavel V. Shatov (Meister) |
| 2019-10-01 | Redesigned core architecture, unified bank structure. All storage blocks now | Pavel V. Shatov (Meister) |
| 2019-10-01 | Major rewrite (different core hierarchy, buses, wrappers, etc). | Pavel V. Shatov (Meister) |
| 2019-10-01 | Implemented the final stage of the Montgomery modular multiplication, i.e. | Pavel V. Shatov (Meister) |
| 2019-10-01 | Further work on the Montgomery modular multiplier. Added the third | Pavel V. Shatov (Meister) |
| 2019-10-01 | Further work on the Montgomery modular multiplier. Can now to the "triangular" | Pavel V. Shatov (Meister) |
| 2019-10-01 | Started working on the pipelined Montgomery modular multiplier. Currently can | Pavel V. Shatov (Meister) |
| 2019-10-01 | Moved to "modexpng_fpga_model" repo, this one was meant for Verilog. | Pavel V. Shatov (Meister) |
| 2019-08-19 | * More cleanup (got rid of .wide. and .narrow.) | Pavel V. Shatov (Meister) |
| 2019-08-19 | * MASSIVE CLEANUP | Pavel V. Shatov (Meister) |
| 2019-08-19 | * Added more micro-operations | Pavel V. Shatov (Meister) |
