diff options
Diffstat (limited to 'rtl/modexpng_storage_manager.v')
| -rw-r--r-- | rtl/modexpng_storage_manager.v | 167 |
1 files changed, 82 insertions, 85 deletions
diff --git a/rtl/modexpng_storage_manager.v b/rtl/modexpng_storage_manager.v index 6b34bed..c39e07a 100644 --- a/rtl/modexpng_storage_manager.v +++ b/rtl/modexpng_storage_manager.v @@ -2,53 +2,20 @@ module modexpng_storage_manager ( clk, rst, - wr_wide_xy_ena, - wr_wide_xy_bank, - wr_wide_xy_addr, - wr_wide_x_din, - wr_wide_y_din, + wr_wide_xy_ena, wr_wide_xy_bank, wr_wide_xy_addr, wr_wide_x_dout, wr_wide_y_dout, + wr_narrow_xy_ena, wr_narrow_xy_bank, wr_narrow_xy_addr, wr_narrow_x_dout, wr_narrow_y_dout, - wr_narrow_xy_ena, - wr_narrow_xy_bank, - wr_narrow_xy_addr, - wr_narrow_x_din, - wr_narrow_y_din, - - ext_wide_xy_ena, - ext_wide_xy_bank, - ext_wide_xy_addr, - ext_wide_x_din, - ext_wide_y_din, - - ext_narrow_xy_ena, - ext_narrow_xy_bank, - ext_narrow_xy_addr, - ext_narrow_x_din, - ext_narrow_y_din, - - rcmb_wide_xy_ena, - rcmb_wide_xy_bank, - rcmb_wide_xy_addr, - rcmb_wide_x_din, - rcmb_wide_y_din, - - rcmb_narrow_xy_ena, - rcmb_narrow_xy_bank, - rcmb_narrow_xy_addr, - rcmb_narrow_x_din, - rcmb_narrow_y_din, - - rdct_wide_xy_bank, - rdct_wide_xy_addr, - rdct_wide_x_din, - rdct_wide_y_din, - rdct_wide_xy_valid, - - rdct_narrow_xy_bank, - rdct_narrow_xy_addr, - rdct_narrow_x_din, - rdct_narrow_y_din, - rdct_narrow_xy_valid + io_narrow_xy_ena, io_narrow_xy_bank, io_narrow_xy_addr, io_narrow_x_din, io_narrow_y_din, + io_wide_xy_ena, io_wide_xy_bank, io_wide_xy_addr, io_wide_x_din, io_wide_y_din, + + rcmb_wide_xy_ena, rcmb_wide_xy_bank, rcmb_wide_xy_addr, rcmb_wide_x_din, rcmb_wide_y_din, + rcmb_narrow_xy_ena, rcmb_narrow_xy_bank, rcmb_narrow_xy_addr, rcmb_narrow_x_din, rcmb_narrow_y_din, + + rdct_wide_xy_bank, rdct_wide_xy_addr, rdct_wide_x_din, rdct_wide_y_din, rdct_wide_xy_valid, + rdct_narrow_xy_bank, rdct_narrow_xy_addr, rdct_narrow_x_din, rdct_narrow_y_din, rdct_narrow_xy_valid, + + wrk_wide_xy_ena, wrk_wide_xy_bank, wrk_wide_xy_addr, wrk_wide_x_din, wrk_wide_y_din, + wrk_narrow_xy_ena, wrk_narrow_xy_bank, wrk_narrow_xy_addr, wrk_narrow_x_din, wrk_narrow_y_din ); @@ -67,51 +34,67 @@ module modexpng_storage_manager output wr_wide_xy_ena; output [BANK_ADDR_W -1:0] wr_wide_xy_bank; output [ OP_ADDR_W -1:0] wr_wide_xy_addr; - output [ WORD_EXT_W -1:0] wr_wide_x_din; - output [ WORD_EXT_W -1:0] wr_wide_y_din; + output [ WORD_EXT_W -1:0] wr_wide_x_dout; + output [ WORD_EXT_W -1:0] wr_wide_y_dout; output wr_narrow_xy_ena; output [BANK_ADDR_W -1:0] wr_narrow_xy_bank; output [ OP_ADDR_W -1:0] wr_narrow_xy_addr; - output [ WORD_EXT_W -1:0] wr_narrow_x_din; - output [ WORD_EXT_W -1:0] wr_narrow_y_din; + output [ WORD_EXT_W -1:0] wr_narrow_x_dout; + output [ WORD_EXT_W -1:0] wr_narrow_y_dout; - input ext_wide_xy_ena; - input [BANK_ADDR_W -1:0] ext_wide_xy_bank; - input [ OP_ADDR_W -1:0] ext_wide_xy_addr; - input [ WORD_EXT_W -1:0] ext_wide_x_din; - input [ WORD_EXT_W -1:0] ext_wide_y_din; - - input ext_narrow_xy_ena; - input [BANK_ADDR_W -1:0] ext_narrow_xy_bank; - input [ OP_ADDR_W -1:0] ext_narrow_xy_addr; - input [ WORD_EXT_W -1:0] ext_narrow_x_din; - input [ WORD_EXT_W -1:0] ext_narrow_y_din; + input io_wide_xy_ena; + input [BANK_ADDR_W -1:0] io_wide_xy_bank; + input [ OP_ADDR_W -1:0] io_wide_xy_addr; + input [ WORD_EXT_W -1:0] io_wide_x_din; + input [ WORD_EXT_W -1:0] io_wide_y_din; + + input io_narrow_xy_ena; + input [BANK_ADDR_W -1:0] io_narrow_xy_bank; + input [ OP_ADDR_W -1:0] io_narrow_xy_addr; + input [ WORD_EXT_W -1:0] io_narrow_x_din; + input [ WORD_EXT_W -1:0] io_narrow_y_din; input rcmb_wide_xy_ena; input [BANK_ADDR_W -1:0] rcmb_wide_xy_bank; - input [ 7:0] rcmb_wide_xy_addr; - input [17:0] rcmb_wide_x_din; - input [17:0] rcmb_wide_y_din; + input [ OP_ADDR_W -1:0] rcmb_wide_xy_addr; + input [ WORD_EXT_W -1:0] rcmb_wide_x_din; + input [ WORD_EXT_W -1:0] rcmb_wide_y_din; input rcmb_narrow_xy_ena; input [BANK_ADDR_W -1:0] rcmb_narrow_xy_bank; - input [ 7:0] rcmb_narrow_xy_addr; - input [17:0] rcmb_narrow_x_din; - input [17:0] rcmb_narrow_y_din; - - input [ 2:0] rdct_wide_xy_bank; - input [ 7:0] rdct_wide_xy_addr; - input [ 17:0] rdct_wide_x_din; - input [ 17:0] rdct_wide_y_din; - input rdct_wide_xy_valid; - - input [ 2:0] rdct_narrow_xy_bank; - input [ 7:0] rdct_narrow_xy_addr; - input [ 17:0] rdct_narrow_x_din; - input [ 17:0] rdct_narrow_y_din; - input rdct_narrow_xy_valid; + input [ OP_ADDR_W -1:0] rcmb_narrow_xy_addr; + input [ WORD_EXT_W -1:0] rcmb_narrow_x_din; + input [ WORD_EXT_W -1:0] rcmb_narrow_y_din; + + input [BANK_ADDR_W -1:0] rdct_wide_xy_bank; + input [ OP_ADDR_W -1:0] rdct_wide_xy_addr; + input [ WORD_EXT_W -1:0] rdct_wide_x_din; + input [ WORD_EXT_W -1:0] rdct_wide_y_din; + input rdct_wide_xy_valid; + + input [BANK_ADDR_W -1:0] rdct_narrow_xy_bank; + input [ OP_ADDR_W -1:0] rdct_narrow_xy_addr; + input [ WORD_EXT_W -1:0] rdct_narrow_x_din; + input [ WORD_EXT_W -1:0] rdct_narrow_y_din; + input rdct_narrow_xy_valid; + input wrk_wide_xy_ena; + input [BANK_ADDR_W -1:0] wrk_wide_xy_bank; + input [ OP_ADDR_W -1:0] wrk_wide_xy_addr; + input [ WORD_EXT_W -1:0] wrk_wide_x_din; + input [ WORD_EXT_W -1:0] wrk_wide_y_din; + + input wrk_narrow_xy_ena; + input [BANK_ADDR_W -1:0] wrk_narrow_xy_bank; + input [ OP_ADDR_W -1:0] wrk_narrow_xy_addr; + input [ WORD_EXT_W -1:0] wrk_narrow_x_din; + input [ WORD_EXT_W -1:0] wrk_narrow_y_din; + + + // + // Output Registers + // reg wr_wide_xy_ena_reg = 1'b0; reg [BANK_ADDR_W -1:0] wr_wide_xy_bank_reg; reg [ OP_ADDR_W -1:0] wr_wide_xy_addr_reg; @@ -186,40 +169,54 @@ module modexpng_storage_manager end endtask + + // + // Write Arbiter + // always @(posedge clk) // if (rst) disable_wide; else begin // - if (ext_wide_xy_ena) enable_wide(ext_wide_xy_bank, ext_wide_xy_addr, ext_wide_x_din, ext_wide_y_din); + if (io_wide_xy_ena) enable_wide(io_wide_xy_bank, io_wide_xy_addr, io_wide_x_din, io_wide_y_din); else if (rcmb_wide_xy_ena) enable_wide(rcmb_wide_xy_bank, rcmb_wide_xy_addr, rcmb_wide_x_din, rcmb_wide_y_din); else if (rdct_wide_xy_valid) enable_wide(rdct_wide_xy_bank, rdct_wide_xy_addr, rdct_wide_x_din, rdct_wide_y_din); + else if (wrk_wide_xy_ena) enable_wide(wrk_wide_xy_bank, wrk_wide_xy_addr, wrk_wide_x_din, wrk_wide_y_din); else disable_wide; // end + + // + // Read Arbiter + // always @(posedge clk) // if (rst) disable_narrow; else begin // - if (ext_narrow_xy_ena) enable_narrow(ext_narrow_xy_bank, ext_narrow_xy_addr, ext_narrow_x_din, ext_narrow_y_din); + if (io_narrow_xy_ena) enable_narrow(io_narrow_xy_bank, io_narrow_xy_addr, io_narrow_x_din, io_narrow_y_din); else if (rcmb_narrow_xy_ena) enable_narrow(rcmb_narrow_xy_bank, rcmb_narrow_xy_addr, rcmb_narrow_x_din, rcmb_narrow_y_din); else if (rdct_narrow_xy_valid) enable_narrow(rdct_narrow_xy_bank, rdct_narrow_xy_addr, rdct_narrow_x_din, rdct_narrow_y_din); + else if (wrk_narrow_xy_ena) enable_narrow(wrk_narrow_xy_bank, wrk_narrow_xy_addr, wrk_narrow_x_din, wrk_narrow_y_din); else disable_narrow; // end + + // + // Port Mapping + // assign wr_wide_xy_ena = wr_wide_xy_ena_reg; assign wr_wide_xy_bank = wr_wide_xy_bank_reg; assign wr_wide_xy_addr = wr_wide_xy_addr_reg; - assign wr_wide_x_din = wr_wide_x_din_reg; - assign wr_wide_y_din = wr_wide_y_din_reg; + assign wr_wide_x_dout = wr_wide_x_din_reg; + assign wr_wide_y_dout = wr_wide_y_din_reg; assign wr_narrow_xy_ena = wr_narrow_xy_ena_reg; assign wr_narrow_xy_bank = wr_narrow_xy_bank_reg; assign wr_narrow_xy_addr = wr_narrow_xy_addr_reg; - assign wr_narrow_x_din = wr_narrow_x_din_reg; - assign wr_narrow_y_din = wr_narrow_y_din_reg; + assign wr_narrow_x_dout = wr_narrow_x_din_reg; + assign wr_narrow_y_dout = wr_narrow_y_din_reg; endmodule |