diff options
Diffstat (limited to 'rtl/modexpng_storage_manager.v')
| -rw-r--r-- | rtl/modexpng_storage_manager.v | 109 |
1 files changed, 54 insertions, 55 deletions
diff --git a/rtl/modexpng_storage_manager.v b/rtl/modexpng_storage_manager.v index fa1e4a1..e5ac83f 100644 --- a/rtl/modexpng_storage_manager.v +++ b/rtl/modexpng_storage_manager.v @@ -43,70 +43,69 @@ module modexpng_storage_manager // // Headers // - `include "../rtl_1/modexpng_parameters_x8_old.vh" + `include "modexpng_parameters.vh" // // Ports // - input clk; - input rst; + input clk; + input rst; - output wr_wide_xy_ena; - output [ 1:0] wr_wide_xy_bank; - output [ 7:0] wr_wide_xy_addr; - output [17:0] wr_wide_x_din; - output [17:0] wr_wide_y_din; + output wr_wide_xy_ena; + output [BANK_ADDR_W -1:0] wr_wide_xy_bank; + output [ OP_ADDR_W -1:0] wr_wide_xy_addr; + output [ WORD_EXT_W -1:0] wr_wide_x_din; + output [ WORD_EXT_W -1:0] wr_wide_y_din; - output wr_narrow_xy_ena; - output [ 1:0] wr_narrow_xy_bank; - output [ 7:0] wr_narrow_xy_addr; - output [17:0] wr_narrow_x_din; - output [17:0] wr_narrow_y_din; + output wr_narrow_xy_ena; + output [BANK_ADDR_W -1:0] wr_narrow_xy_bank; + output [ OP_ADDR_W -1:0] wr_narrow_xy_addr; + output [ WORD_EXT_W -1:0] wr_narrow_x_din; + output [ WORD_EXT_W -1:0] wr_narrow_y_din; - input ext_wide_xy_ena; - input [ 1:0] ext_wide_xy_bank; - input [ 7:0] ext_wide_xy_addr; - input [17:0] ext_wide_x_din; - input [17:0] ext_wide_y_din; + input ext_wide_xy_ena; + input [BANK_ADDR_W -1:0] ext_wide_xy_bank; + input [ OP_ADDR_W -1:0] ext_wide_xy_addr; + input [ WORD_EXT_W -1:0] ext_wide_x_din; + input [ WORD_EXT_W -1:0] ext_wide_y_din; - input ext_narrow_xy_ena; - input [ 1:0] ext_narrow_xy_bank; - input [ 7:0] ext_narrow_xy_addr; - input [17:0] ext_narrow_x_din; - input [17:0] ext_narrow_y_din; + input ext_narrow_xy_ena; + input [BANK_ADDR_W -1:0] ext_narrow_xy_bank; + input [ OP_ADDR_W -1:0] ext_narrow_xy_addr; + input [ WORD_EXT_W -1:0] ext_narrow_x_din; + input [ WORD_EXT_W -1:0] ext_narrow_y_din; input rcmb_wide_xy_ena; - input [ 1:0] rcmb_wide_xy_bank; + input [ BANK_ADDR_W -1:0] rcmb_wide_xy_bank; input [ 7:0] rcmb_wide_xy_addr; input [17:0] rcmb_wide_x_din; input [17:0] rcmb_wide_y_din; input rcmb_narrow_xy_ena; - input [ 1:0] rcmb_narrow_xy_bank; + input [ BANK_ADDR_W -1:0] rcmb_narrow_xy_bank; input [ 7:0] rcmb_narrow_xy_addr; input [17:0] rcmb_narrow_x_din; input [17:0] rcmb_narrow_y_din; - - reg wr_wide_xy_ena_reg = 1'b0; - reg [ 1:0] wr_wide_xy_bank_reg; - reg [ 7:0] wr_wide_xy_addr_reg; - reg [17:0] wr_wide_x_din_reg; - reg [17:0] wr_wide_y_din_reg; + reg wr_wide_xy_ena_reg = 1'b0; + reg [BANK_ADDR_W -1:0] wr_wide_xy_bank_reg; + reg [ OP_ADDR_W -1:0] wr_wide_xy_addr_reg; + reg [ WORD_EXT_W -1:0] wr_wide_x_din_reg; + reg [ WORD_EXT_W -1:0] wr_wide_y_din_reg; - reg wr_narrow_xy_ena_reg = 1'b0; - reg [ 1:0] wr_narrow_xy_bank_reg; - reg [ 7:0] wr_narrow_xy_addr_reg; - reg [17:0] wr_narrow_x_din_reg; - reg [17:0] wr_narrow_y_din_reg; + reg wr_narrow_xy_ena_reg = 1'b0; + reg [BANK_ADDR_W -1:0] wr_narrow_xy_bank_reg; + reg [ OP_ADDR_W -1:0] wr_narrow_xy_addr_reg; + reg [ WORD_EXT_W -1:0] wr_narrow_x_din_reg; + reg [ WORD_EXT_W -1:0] wr_narrow_y_din_reg; task _update_wide; - input xy_ena; - input [ 1:0] xy_bank; - input [ 7:0] xy_addr; - input [17:0] x_din; - input [17:0] y_din; + input xy_ena; + input [BANK_ADDR_W -1:0] xy_bank; + input [ OP_ADDR_W -1:0] xy_addr; + input [ WORD_EXT_W -1:0] x_din; + input [ WORD_EXT_W -1:0] y_din; begin wr_wide_xy_ena_reg <= xy_ena; wr_wide_xy_bank_reg <= xy_bank; @@ -118,10 +117,10 @@ module modexpng_storage_manager task _update_narrow; input xy_ena; - input [ 1:0] xy_bank; - input [ 7:0] xy_addr; - input [17:0] x_din; - input [17:0] y_din; + input [BANK_ADDR_W -1:0] xy_bank; + input [ OP_ADDR_W -1:0] xy_addr; + input [ WORD_EXT_W -1:0] x_din; + input [ WORD_EXT_W -1:0] y_din; begin wr_narrow_xy_ena_reg <= xy_ena; wr_narrow_xy_bank_reg <= xy_bank; @@ -132,20 +131,20 @@ module modexpng_storage_manager endtask task enable_wide; - input [ 1:0] xy_bank; - input [ 7:0] xy_addr; - input [17:0] x_din; - input [17:0] y_din; + input [BANK_ADDR_W -1:0] xy_bank; + input [ OP_ADDR_W -1:0] xy_addr; + input [ WORD_EXT_W -1:0] x_din; + input [ WORD_EXT_W -1:0] y_din; begin _update_wide(1'b1, xy_bank, xy_addr, x_din, y_din); end endtask task enable_narrow; - input [ 1:0] xy_bank; - input [ 7:0] xy_addr; - input [17:0] x_din; - input [17:0] y_din; + input [BANK_ADDR_W -1:0] xy_bank; + input [ OP_ADDR_W -1:0] xy_addr; + input [ WORD_EXT_W -1:0] x_din; + input [ WORD_EXT_W -1:0] y_din; begin _update_narrow(1'b1, xy_bank, xy_addr, x_din, y_din); end @@ -153,13 +152,13 @@ module modexpng_storage_manager task disable_wide; begin - _update_wide(1'b0, 2'bXX, 8'hXX, {18{1'bX}}, {18{1'bX}}); + _update_wide(1'b0, BANK_DONT_CARE, OP_ADDR_DONT_CARE, WORD_EXT_DONT_CARE, WORD_EXT_DONT_CARE); end endtask task disable_narrow; begin - _update_narrow(1'b0, 2'bXX, 8'hXX, {18{1'bX}}, {18{1'bX}}); + _update_narrow(1'b0, BANK_DONT_CARE, OP_ADDR_DONT_CARE, WORD_EXT_DONT_CARE, WORD_EXT_DONT_CARE); end endtask |