diff options
Diffstat (limited to 'rtl/modexpng_storage_block.v')
| -rw-r--r-- | rtl/modexpng_storage_block.v | 126 |
1 files changed, 112 insertions, 14 deletions
diff --git a/rtl/modexpng_storage_block.v b/rtl/modexpng_storage_block.v index f1d5ae2..19601ef 100644 --- a/rtl/modexpng_storage_block.v +++ b/rtl/modexpng_storage_block.v @@ -1,6 +1,6 @@ module modexpng_storage_block ( - clk, clk_bus, rst, + clk, rst, wr_wide_xy_ena, wr_wide_xy_bank, @@ -29,7 +29,19 @@ module modexpng_storage_block rd_narrow_xy_bank, rd_narrow_xy_addr, rd_narrow_x_dout, - rd_narrow_y_dout + rd_narrow_y_dout, + + wrk_wide_xy_ena, + wrk_wide_xy_bank, + wrk_wide_xy_addr, + wrk_wide_x_dout, + wrk_wide_y_dout, + + wrk_narrow_xy_ena, + wrk_narrow_xy_bank, + wrk_narrow_xy_addr, + wrk_narrow_x_dout, + wrk_narrow_y_dout ); // @@ -42,7 +54,6 @@ module modexpng_storage_block // Ports // input clk; - input clk_bus; input rst; input wr_wide_xy_ena; @@ -74,6 +85,18 @@ module modexpng_storage_block output [ WORD_EXT_W -1:0] rd_narrow_x_dout; output [ WORD_EXT_W -1:0] rd_narrow_y_dout; + input wrk_wide_xy_ena; + input [ BANK_ADDR_W -1:0] wrk_wide_xy_bank; + input [ OP_ADDR_W -1:0] wrk_wide_xy_addr; + output [ WORD_EXT_W -1:0] wrk_wide_x_dout; + output [ WORD_EXT_W -1:0] wrk_wide_y_dout; + + input wrk_narrow_xy_ena; + input [ BANK_ADDR_W -1:0] wrk_narrow_xy_bank; + input [ OP_ADDR_W -1:0] wrk_narrow_xy_addr; + output [ WORD_EXT_W -1:0] wrk_narrow_x_dout; + output [ WORD_EXT_W -1:0] wrk_narrow_y_dout; + // // Internal Registers @@ -81,6 +104,8 @@ module modexpng_storage_block reg rd_wide_xy_reg_ena = 1'b0; reg rd_wide_xy_reg_ena_aux = 1'b0; reg rd_narrow_xy_reg_ena = 1'b0; + reg wrk_wide_xy_reg_ena = 1'b0; + reg wrk_narrow_xy_reg_ena = 1'b0; always @(posedge clk) // @@ -88,10 +113,14 @@ module modexpng_storage_block rd_wide_xy_reg_ena <= 1'b0; rd_wide_xy_reg_ena_aux <= 1'b0; rd_narrow_xy_reg_ena <= 1'b0; + wrk_wide_xy_reg_ena <= 1'b0; + wrk_narrow_xy_reg_ena <= 1'b0; end else begin rd_wide_xy_reg_ena <= rd_wide_xy_ena; rd_wide_xy_reg_ena_aux <= rd_wide_xy_ena_aux; rd_narrow_xy_reg_ena <= rd_narrow_xy_ena; + wrk_wide_xy_reg_ena <= wrk_wide_xy_ena; + wrk_narrow_xy_reg_ena <= wrk_narrow_xy_ena; end // @@ -102,22 +131,26 @@ module modexpng_storage_block wire [BANK_ADDR_W + OP_ADDR_W -1:0] rd_narrow_xy_offset; wire [BANK_ADDR_W + OP_ADDR_W -1:0] wr_wide_xy_offset; wire [BANK_ADDR_W + OP_ADDR_W -1:0] wr_narrow_xy_offset; + wire [BANK_ADDR_W + OP_ADDR_W -1:0] wrk_wide_xy_offset; + wire [BANK_ADDR_W + OP_ADDR_W -1:0] wrk_narrow_xy_offset; assign rd_wide_xy_offset_aux = {rd_wide_xy_bank_aux, rd_wide_xy_addr_aux}; - assign rd_narrow_xy_offset = {rd_narrow_xy_bank, rd_narrow_xy_addr}; - assign wr_wide_xy_offset = {wr_wide_xy_bank, wr_wide_xy_addr}; - assign wr_narrow_xy_offset = {wr_narrow_xy_bank, wr_narrow_xy_addr}; + assign rd_narrow_xy_offset = {rd_narrow_xy_bank, rd_narrow_xy_addr }; + assign wr_wide_xy_offset = {wr_wide_xy_bank, wr_wide_xy_addr }; + assign wr_narrow_xy_offset = {wr_narrow_xy_bank, wr_narrow_xy_addr }; + assign wrk_wide_xy_offset = {wrk_wide_xy_bank, wrk_wide_xy_addr }; + assign wrk_narrow_xy_offset = {wrk_narrow_xy_bank, wrk_narrow_xy_addr }; // // "Wide" Storage // genvar z; generate for (z=0; z<NUM_MULTS_HALF; z=z+1) - begin : gen_wide_bram + begin : gen_wide // assign rd_wide_xy_offset[z] = {1'b0, rd_wide_xy_bank, rd_wide_xy_addr[z*OP_ADDR_W +: OP_ADDR_W]}; // - modexpng_sdp_36k_x18_wrapper wide_bram_x + modexpng_sdp_36k_x18_wrapper wide_x ( .clk (clk), @@ -132,7 +165,7 @@ module modexpng_storage_block .doutb (rd_wide_x_dout[z*WORD_EXT_W +: WORD_EXT_W]) ); // - modexpng_sdp_36k_x18_wrapper wide_bram_y + modexpng_sdp_36k_x18_wrapper wide_y ( .clk (clk), @@ -151,9 +184,42 @@ module modexpng_storage_block endgenerate // - // Auxilary Storage + // Worker "Wide" Storage + // + modexpng_sdp_36k_x18_wrapper wrk_wide_x + ( + .clk (clk), + + .ena (wr_wide_xy_ena), + .wea (wr_wide_xy_ena), + .addra (wr_wide_xy_offset), + .dina (wr_wide_x_din), + + .enb (wrk_wide_xy_ena), + .regceb (wrk_wide_xy_reg_ena), + .addrb (wrk_wide_xy_offset), + .doutb (wrk_wide_x_dout) + ); // - modexpng_sdp_36k_x18_wrapper wide_bram_x_aux + modexpng_sdp_36k_x18_wrapper wrk_wide_y + ( + .clk (clk), + + .ena (wr_wide_xy_ena), + .wea (wr_wide_xy_ena), + .addra (wr_wide_xy_offset), + .dina (wr_wide_y_din), + + .enb (wrk_wide_xy_ena), + .regceb (wrk_wide_xy_reg_ena), + .addrb (wrk_wide_xy_offset), + .doutb (wrk_wide_y_dout) + ); + + // + // Auxilary "Wide" Storage + // + modexpng_sdp_36k_x18_wrapper wide_x_aux ( .clk (clk), @@ -168,7 +234,7 @@ module modexpng_storage_block .doutb (rd_wide_x_dout_aux) ); // - modexpng_sdp_36k_x18_wrapper wide_bram_y_aux + modexpng_sdp_36k_x18_wrapper wide_y_aux ( .clk (clk), @@ -186,7 +252,7 @@ module modexpng_storage_block // // "Narrow" Storage // - modexpng_sdp_36k_x18_wrapper narrow_bram_x + modexpng_sdp_36k_x18_wrapper narrow_x ( .clk (clk), @@ -201,7 +267,7 @@ module modexpng_storage_block .doutb (rd_narrow_x_dout) ); - modexpng_sdp_36k_x18_wrapper narrow_bram_y + modexpng_sdp_36k_x18_wrapper narrow_y ( .clk (clk), @@ -215,7 +281,39 @@ module modexpng_storage_block .addrb (rd_narrow_xy_offset), .doutb (rd_narrow_y_dout) ); + + // + // Worker "Narrow" Storage + // + modexpng_sdp_36k_x18_wrapper wrk_narrow_x + ( + .clk (clk), + + .ena (wr_narrow_xy_ena), + .wea (wr_narrow_xy_ena), + .addra (wr_narrow_xy_offset), + .dina (wr_narrow_x_din), + + .enb (wrk_narrow_xy_ena), + .regceb (wrk_narrow_xy_reg_ena), + .addrb (wrk_narrow_xy_offset), + .doutb (wrk_narrow_x_dout) + ); + + modexpng_sdp_36k_x18_wrapper wrk_narrow_y + ( + .clk (clk), + .ena (wr_narrow_xy_ena), + .wea (wr_narrow_xy_ena), + .addra (wr_narrow_xy_offset), + .dina (wr_narrow_y_din), + + .enb (wrk_narrow_xy_ena), + .regceb (wrk_narrow_xy_reg_ena), + .addrb (wrk_narrow_xy_offset), + .doutb (wrk_narrow_y_dout) + ); endmodule |