diff options
Diffstat (limited to 'rtl/modexpng_storage_block.v')
| -rw-r--r-- | rtl/modexpng_storage_block.v | 136 |
1 files changed, 63 insertions, 73 deletions
diff --git a/rtl/modexpng_storage_block.v b/rtl/modexpng_storage_block.v index d6f9fb1..be04c7c 100644 --- a/rtl/modexpng_storage_block.v +++ b/rtl/modexpng_storage_block.v @@ -32,49 +32,46 @@ module modexpng_storage_block rd_narrow_y_dout ); - // // Headers // - `include "../rtl_1/modexpng_parameters_x8_old.vh" - + `include "modexpng_parameters.vh" // // Ports // - input clk; - input rst; - - input wr_wide_xy_ena; - input [ 1:0] wr_wide_xy_bank; - input [ 7:0] wr_wide_xy_addr; - input [17:0] wr_wide_x_din; - input [17:0] wr_wide_y_din; + input clk; + input rst; + + input wr_wide_xy_ena; + input [ BANK_ADDR_W -1:0] wr_wide_xy_bank; + input [ OP_ADDR_W -1:0] wr_wide_xy_addr; + input [ WORD_EXT_W -1:0] wr_wide_x_din; + input [ WORD_EXT_W -1:0] wr_wide_y_din; - input wr_narrow_xy_ena; - input [ 1:0] wr_narrow_xy_bank; - input [ 7:0] wr_narrow_xy_addr; - input [17:0] wr_narrow_x_din; - input [17:0] wr_narrow_y_din; - - input rd_wide_xy_ena; - input rd_wide_xy_ena_aux; - input [ 1:0] rd_wide_xy_bank; - input [ 1:0] rd_wide_xy_bank_aux; - input [ 8*NUM_MULTS/2-1:0] rd_wide_xy_addr; - input [ 8-1:0] rd_wide_xy_addr_aux; - output [18*NUM_MULTS/2-1:0] rd_wide_x_dout; - output [18*NUM_MULTS/2-1:0] rd_wide_y_dout; - output [ 18-1:0] rd_wide_x_dout_aux; - output [ 18-1:0] rd_wide_y_dout_aux; + input wr_narrow_xy_ena; + input [ BANK_ADDR_W -1:0] wr_narrow_xy_bank; + input [ OP_ADDR_W -1:0] wr_narrow_xy_addr; + input [ WORD_EXT_W -1:0] wr_narrow_x_din; + input [ WORD_EXT_W -1:0] wr_narrow_y_din; + + input rd_wide_xy_ena; + input rd_wide_xy_ena_aux; + input [ BANK_ADDR_W -1:0] rd_wide_xy_bank; + input [ BANK_ADDR_W -1:0] rd_wide_xy_bank_aux; + input [NUM_MULTS_HALF * OP_ADDR_W -1:0] rd_wide_xy_addr; + input [ OP_ADDR_W -1:0] rd_wide_xy_addr_aux; + output [NUM_MULTS_HALF * WORD_EXT_W -1:0] rd_wide_x_dout; + output [NUM_MULTS_HALF * WORD_EXT_W -1:0] rd_wide_y_dout; + output [ WORD_EXT_W -1:0] rd_wide_x_dout_aux; + output [ WORD_EXT_W -1:0] rd_wide_y_dout_aux; - input rd_narrow_xy_ena; - input [ 1:0] rd_narrow_xy_bank; - input [ 7:0] rd_narrow_xy_addr; - output [18-1:0] rd_narrow_x_dout; - output [18-1:0] rd_narrow_y_dout; + input rd_narrow_xy_ena; + input [ BANK_ADDR_W -1:0] rd_narrow_xy_bank; + input [ OP_ADDR_W -1:0] rd_narrow_xy_addr; + output [ WORD_EXT_W -1:0] rd_narrow_x_dout; + output [ WORD_EXT_W -1:0] rd_narrow_y_dout; - // // Internal Registers // @@ -82,43 +79,44 @@ module modexpng_storage_block reg rd_wide_xy_reg_ena_aux = 1'b0; reg rd_narrow_xy_reg_ena = 1'b0; - always @(posedge clk) begin - // - rd_wide_xy_reg_ena <= rst ? 1'b0 : rd_wide_xy_ena; - rd_wide_xy_reg_ena_aux <= rst ? 1'b0 : rd_wide_xy_ena_aux; - rd_narrow_xy_reg_ena <= rst ? 1'b0 : rd_narrow_xy_ena; + always @(posedge clk) // - end - + if (rst) begin + rd_wide_xy_reg_ena <= 1'b0; + rd_wide_xy_reg_ena_aux <= 1'b0; + rd_narrow_xy_reg_ena <= 1'b0; + end else begin + rd_wide_xy_reg_ena <= rd_wide_xy_ena; + rd_wide_xy_reg_ena_aux <= rd_wide_xy_ena_aux; + rd_narrow_xy_reg_ena <= rd_narrow_xy_ena; + end // // Helper Signals // - wire [2+8-1:0] wr_wide_xy_offset; - wire [2+8-1:0] rd_wide_xy_offset[0:NUM_MULTS/2-1]; - wire [2+8-1:0] rd_wide_xy_offset_aux; - wire [2+8-1:0] wr_narrow_xy_offset; - wire [2+8-1:0] rd_narrow_xy_offset; + wire [BANK_ADDR_W + OP_ADDR_W -1:0] rd_wide_xy_offset[0:NUM_MULTS_HALF-1]; + wire [BANK_ADDR_W + OP_ADDR_W -1:0] rd_wide_xy_offset_aux; + wire [BANK_ADDR_W + OP_ADDR_W -1:0] rd_narrow_xy_offset; + wire [BANK_ADDR_W + OP_ADDR_W -1:0] wr_wide_xy_offset; + wire [BANK_ADDR_W + OP_ADDR_W -1:0] wr_narrow_xy_offset; - assign wr_wide_xy_offset = {wr_wide_xy_bank, wr_wide_xy_addr}; assign rd_wide_xy_offset_aux = {rd_wide_xy_bank_aux, rd_wide_xy_addr_aux}; - assign wr_narrow_xy_offset = {wr_narrow_xy_bank, wr_narrow_xy_addr}; assign rd_narrow_xy_offset = {rd_narrow_xy_bank, rd_narrow_xy_addr}; - + assign wr_wide_xy_offset = {wr_wide_xy_bank, wr_wide_xy_addr}; + assign wr_narrow_xy_offset = {wr_narrow_xy_bank, wr_narrow_xy_addr}; // // "Wide" Storage // genvar z; - generate for (z=0; z<(NUM_MULTS/2); z=z+1) + generate for (z=0; z<NUM_MULTS_HALF; z=z+1) begin : gen_wide_bram // - assign rd_wide_xy_offset[z] = {rd_wide_xy_bank, rd_wide_xy_addr[8*z+:8]}; + assign rd_wide_xy_offset[z] = {1'b0, rd_wide_xy_bank, rd_wide_xy_addr[z*OP_ADDR_W +: OP_ADDR_W]}; // - ip_bram_18k wide_bram_x + modexpng_sdp_36k_wrapper wide_bram_x ( - .clka (clk), - .clkb (clk), + .clk (clk), .ena (wr_wide_xy_ena), .wea (wr_wide_xy_ena), @@ -128,13 +126,12 @@ module modexpng_storage_block .enb (rd_wide_xy_ena), .regceb (rd_wide_xy_reg_ena), .addrb (rd_wide_xy_offset[z]), - .doutb (rd_wide_x_dout[18*z+:18]) + .doutb (rd_wide_x_dout[z*WORD_EXT_W +: WORD_EXT_W]) ); // - ip_bram_18k wide_bram_y + modexpng_sdp_36k_wrapper wide_bram_y ( - .clka (clk), - .clkb (clk), + .clk (clk), .ena (wr_wide_xy_ena), .wea (wr_wide_xy_ena), @@ -144,20 +141,18 @@ module modexpng_storage_block .enb (rd_wide_xy_ena), .regceb (rd_wide_xy_reg_ena), .addrb (rd_wide_xy_offset[z]), - .doutb (rd_wide_y_dout[18*z+:18]) + .doutb (rd_wide_y_dout[z*WORD_EXT_W +: WORD_EXT_W]) ); // end endgenerate - // // Auxilary Storage // - ip_bram_18k wide_bram_x_aux + modexpng_sdp_36k_wrapper wide_bram_x_aux ( - .clka (clk), - .clkb (clk), + .clk (clk), .ena (wr_wide_xy_ena), .wea (wr_wide_xy_ena), @@ -170,10 +165,9 @@ module modexpng_storage_block .doutb (rd_wide_x_dout_aux) ); // - ip_bram_18k wide_bram_y_aux + modexpng_sdp_36k_wrapper wide_bram_y_aux ( - .clka (clk), - .clkb (clk), + .clk (clk), .ena (wr_wide_xy_ena), .wea (wr_wide_xy_ena), @@ -186,14 +180,12 @@ module modexpng_storage_block .doutb (rd_wide_y_dout_aux) ); - // // "Narrow" Storage // - ip_bram_18k narrow_bram_x + modexpng_sdp_36k_wrapper narrow_bram_x ( - .clka (clk), - .clkb (clk), + .clk (clk), .ena (wr_narrow_xy_ena), .wea (wr_narrow_xy_ena), @@ -206,10 +198,9 @@ module modexpng_storage_block .doutb (rd_narrow_x_dout) ); - ip_bram_18k narrow_bram_y + modexpng_sdp_36k_wrapper narrow_bram_y ( - .clka (clk), - .clkb (clk), + .clk (clk), .ena (wr_narrow_xy_ena), .wea (wr_narrow_xy_ena), @@ -222,5 +213,4 @@ module modexpng_storage_block .doutb (rd_narrow_y_dout) ); - endmodule |