diff options
author | Pavel V. Shatov (Meister) <meisterpaul1@yandex.ru> | 2019-10-21 13:04:07 +0300 |
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committer | Pavel V. Shatov (Meister) <meisterpaul1@yandex.ru> | 2019-10-21 13:04:07 +0300 |
commit | 72902f5b40ac695786f5103d2a5a456c6c7ee83f (patch) | |
tree | 59a644e74fa4fdc25c92b8d261150ef4899323f5 /rtl/modexpng_sdp_36k_x16_x32_wrapper_generic.v | |
parent | 9eac252242c69e51a38a9a88c87b564dd40b6257 (diff) |
Redesigned the testbench. Core clock does not necessarily need to be twice
faster than the bus clock now. It can be the same, or say four times faster.
Diffstat (limited to 'rtl/modexpng_sdp_36k_x16_x32_wrapper_generic.v')
-rw-r--r-- | rtl/modexpng_sdp_36k_x16_x32_wrapper_generic.v | 66 |
1 files changed, 32 insertions, 34 deletions
diff --git a/rtl/modexpng_sdp_36k_x16_x32_wrapper_generic.v b/rtl/modexpng_sdp_36k_x16_x32_wrapper_generic.v index 034b00b..3797e41 100644 --- a/rtl/modexpng_sdp_36k_x16_x32_wrapper_generic.v +++ b/rtl/modexpng_sdp_36k_x16_x32_wrapper_generic.v @@ -34,42 +34,40 @@ module modexpng_sdp_36k_x16_x32_wrapper_generic // - // BRAM_SDP_MACRO + // Memory // - BRAM_SDP_MACRO # - ( - .DEVICE ("7SERIES"), - - .BRAM_SIZE ("36Kb"), - - .WRITE_WIDTH (BUS_DATA_W), - .READ_WIDTH (WORD_W), - - .DO_REG (1), - .WRITE_MODE ("READ_FIRST"), - - .SRVAL (72'h000000000000000000), - .INIT (72'h000000000000000000), - - .INIT_FILE ("NONE"), - .SIM_COLLISION_CHECK ("NONE") - ) - BRAM_SDP_MACRO_inst - ( - .RST (1'b0), + reg [BUS_DATA_W -1:0] mem[0:2**(BANK_ADDR_W+BUS_OP_ADDR_W)-1]; + + // + // Write Port + // + always @(posedge clk_bus) + // + if (ena && wea) + mem[addra] <= dina; + + // + // Read Port + // + reg [WORD_W -1:0] doutb_reg1; + reg [WORD_W -1:0] doutb_reg2; + + assign doutb = doutb_reg2; + + wire [BUS_DATA_W -1:0] mem_addrb = mem[addrb[BANK_ADDR_W + OP_ADDR_W -1:1]]; + + wire [ WORD_W -1:0] mem_addrb_msb = mem_addrb[ BUS_DATA_W -1:WORD_W]; + wire [ WORD_W -1:0] mem_addrb_lsb = mem_addrb[ WORD_W -1: 0]; - .WRCLK (clk_bus), - .WREN (ena), - .WE ({4{wea}}), - .WRADDR (addra), - .DI (dina), - - .RDCLK (clk), - .RDEN (enb), - .REGCE (regceb), - .RDADDR (addrb), - .DO (doutb) - ); + always @(posedge clk) + // + if (enb) + doutb_reg1 <= addrb[0] ? mem_addrb_msb : mem_addrb_lsb; + + always @(posedge clk) + // + if (regceb) + doutb_reg2 <= doutb_reg1; endmodule |