Further work:

 - added core wrapper
 - fixed module resets across entire core (all the resets are now consistently
   active-low)
 - continued refactoring

1 files changed, 25 insertions, 26 deletions

diff --git a/rtl/modexpng_recombinator_block.v b/rtl/modexpng_recombinator_block.v
index f698c18..7a9154a 100644
--- a/rtl/modexpng_recombinator_block.v
+++ b/rtl/modexpng_recombinator_block.v
@@ -1,6 +1,6 @@
 module modexpng_recombinator_block
 (
-    clk, rst,
+    clk, rst_n,
     ena, rdy,
     fsm_state_next,
     word_index_last,
@@ -18,15 +18,14 @@ module modexpng_recombinator_block
     // Headers
     //
     `include "modexpng_parameters.vh"
-    `include "../rtl_1/modexpng_mmm_fsm_old.vh"
-    //`include "../rtl_1/modexpng_parameters_x8_old.vh"
+    `include "modexpng_mmm_dual_fsm.vh"
 
 
     input                        clk;
-    input                        rst;
+    input                        rst_n;
     input                        ena;
     output                       rdy;
-    input  [FSM_STATE_WIDTH-1:0] fsm_state_next;
+    input  [MMM_FSM_STATE_W-1:0] fsm_state_next;
     input [7:0]                  word_index_last;
     input                        dsp_xy_ce_p;
     input  [9*47-1:0] dsp_x_p;
@@ -83,10 +82,10 @@ module modexpng_recombinator_block
     //
     reg dsp_xy_ce_p_dly1 = 1'b0;
 
-    always @(posedge clk)
+    always @(posedge clk or negedge rst_n)
         //
-        if (rst) dsp_xy_ce_p_dly1 <= 1'b0;
-        else     dsp_xy_ce_p_dly1 <= dsp_xy_ce_p;
+        if (!rst_n) dsp_xy_ce_p_dly1 <= 1'b0;
+        else        dsp_xy_ce_p_dly1 <= dsp_xy_ce_p;
 
 
     //
@@ -144,9 +143,9 @@ module modexpng_recombinator_block
        if (ena)
            //
            case (fsm_state_next)
-               FSM_STATE_MULT_SQUARE_COL_0_BUSY:        rcmb_mode <= 2'd1;
-               FSM_STATE_MULT_TRIANGLE_COL_0_BUSY:      rcmb_mode <= 2'd2;
-               FSM_STATE_MULT_RECTANGLE_COL_0_BUSY:     rcmb_mode <= 2'd3;
+               MMM_FSM_STATE_MULT_SQUARE_COL_0_BUSY:        rcmb_mode <= 2'd1;
+               MMM_FSM_STATE_MULT_TRIANGLE_COL_0_BUSY:      rcmb_mode <= 2'd2;
+               MMM_FSM_STATE_MULT_RECTANGLE_COL_0_BUSY:     rcmb_mode <= 2'd3;
                default:                                 rcmb_mode <= 2'd0;
            endcase
 
@@ -583,7 +582,7 @@ module modexpng_recombinator_block
             rcmb_xy_lsb_ce_purge <= {1'b0, rcmb_xy_lsb_ce_purge[2:1]};
         //
         if (xy_purge_latch_msb && xy_bitmap_latch_msb[0] && !xy_bitmap_latch_msb[1])
-            rcmb_xy_msb_ce_purge = 2'b11;
+            rcmb_xy_msb_ce_purge <= 2'b11;
         else
             rcmb_xy_msb_ce_purge <= {1'b0, rcmb_xy_msb_ce_purge[1]};
         //
@@ -628,10 +627,10 @@ module modexpng_recombinator_block
         //
         case (fsm_state_next)
             //
-            FSM_STATE_MULT_SQUARE_COL_0_TRIG,
-            FSM_STATE_MULT_SQUARE_COL_N_TRIG,
-            FSM_STATE_MULT_SQUARE_COL_0_BUSY,
-            FSM_STATE_MULT_SQUARE_COL_N_BUSY: begin
+            MMM_FSM_STATE_MULT_SQUARE_COL_0_TRIG,
+            MMM_FSM_STATE_MULT_SQUARE_COL_N_TRIG,
+            MMM_FSM_STATE_MULT_SQUARE_COL_0_BUSY,
+            MMM_FSM_STATE_MULT_SQUARE_COL_N_BUSY: begin
                 //
                 xy_valid_lsb_adv [6] <= calc_square_valid_lsb (col_index, col_index_last, rd_narrow_xy_bank, rd_narrow_xy_addr);
                 xy_aux_lsb_adv   [6] <= 1'b0;
@@ -645,10 +644,10 @@ module modexpng_recombinator_block
                 //
             end
             //
-            FSM_STATE_MULT_TRIANGLE_COL_0_TRIG,
-            FSM_STATE_MULT_TRIANGLE_COL_N_TRIG,
-            FSM_STATE_MULT_TRIANGLE_COL_0_BUSY,
-            FSM_STATE_MULT_TRIANGLE_COL_N_BUSY: begin
+            MMM_FSM_STATE_MULT_TRIANGLE_COL_0_TRIG,
+            MMM_FSM_STATE_MULT_TRIANGLE_COL_N_TRIG,
+            MMM_FSM_STATE_MULT_TRIANGLE_COL_0_BUSY,
+            MMM_FSM_STATE_MULT_TRIANGLE_COL_N_BUSY: begin
                 //
                 xy_valid_lsb_adv [6] <= calc_triangle_valid_lsb (col_index, col_index_last, rd_narrow_xy_bank, rd_narrow_xy_addr);
                 xy_aux_lsb_adv   [6] <= calc_triangle_aux_lsb   (col_index, col_index_last, rd_narrow_xy_bank, rd_narrow_xy_addr);
@@ -662,10 +661,10 @@ module modexpng_recombinator_block
                 //
             end
             //
-            FSM_STATE_MULT_RECTANGLE_COL_0_TRIG,
-            FSM_STATE_MULT_RECTANGLE_COL_N_TRIG,
-            FSM_STATE_MULT_RECTANGLE_COL_0_BUSY,
-            FSM_STATE_MULT_RECTANGLE_COL_N_BUSY: begin
+            MMM_FSM_STATE_MULT_RECTANGLE_COL_0_TRIG,
+            MMM_FSM_STATE_MULT_RECTANGLE_COL_N_TRIG,
+            MMM_FSM_STATE_MULT_RECTANGLE_COL_0_BUSY,
+            MMM_FSM_STATE_MULT_RECTANGLE_COL_N_BUSY: begin
                 //
                 xy_valid_lsb_adv [6] <= calc_rectangle_valid_lsb (col_index, col_index_last, rd_narrow_xy_bank, rd_narrow_xy_addr);
                 xy_aux_lsb_adv   [6] <= 1'b0;
@@ -772,9 +771,9 @@ module modexpng_recombinator_block
     reg rcmb_xy_lsb_valid = 1'b0;
     reg rcmb_xy_msb_valid = 1'b0;
 
-    always @(posedge clk)
+    always @(posedge clk or negedge rst_n)
         //
-        if (rst) begin
+        if (!rst_n) begin
             rcmb_xy_lsb_valid <= 1'b0;
             rcmb_xy_msb_valid <= 1'b0;        
         end else begin