1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
|
`timescale 1ns / 1ps
module modexpa7_simple_fifo #
(
parameter BUS_WIDTH = 128,
parameter DEPTH_BITS = 2
)
(
input clk,
input rst,
input wr_en,
input rd_en,
input [BUS_WIDTH-1:0] d_in,
output [BUS_WIDTH-1:0] d_out
);
//
// Locals
//
localparam NUM_WORDS = 2 ** DEPTH_BITS;
localparam [DEPTH_BITS:0] PTR_ZERO = {DEPTH_BITS{1'b0}};
localparam [DEPTH_BITS:0] PTR_LAST = {DEPTH_BITS{1'b1}};
//
// Memory
//
(* RAM_STYLE="DISTRIBUTED" *)
reg [BUS_WIDTH-1:0] fifo[0:NUM_WORDS-1];
//
// Pointers
//
reg [DEPTH_BITS-1:0] ptr_wr;
reg [DEPTH_BITS-1:0] ptr_rd;
//
// Output
//
reg [BUS_WIDTH-1:0] d_out_reg;
assign d_out = d_out_reg;
//
// Write Pointer
//
always @(posedge clk)
//
if (rst) ptr_wr <= PTR_ZERO;
else if (wr_en) ptr_wr <= ptr_wr + 1'b1;
//
// Read Pointer
//
always @(posedge clk)
//
if (rst) ptr_rd <= PTR_ZERO;
else if (rd_en) ptr_rd <= ptr_rd + 1'b1;
//
// Read Logic
//
always @(posedge clk)
//
if (rst) d_out_reg <= {BUS_WIDTH{1'b0}};
else if (rd_en) d_out_reg <= fifo[ptr_rd];
//
// Write Logic
//
always @(posedge clk)
//
if (!rst && wr_en) fifo[ptr_wr] <= d_in;
/*
generic_dpram #(aw,dw) u0(
.rclk( clk ),
.rrst( !rst ),
.rce( 1'b1 ),
.oe( 1'b1 ),
.raddr( rp ),
.do( dout ),
.wclk( clk ),
.wrst( !rst ),
.wce( 1'b1 ),
.we( we ),
.waddr( wp ),
.di( din )
);
////////////////////////////////////////////////////////////////////
//
// Misc Logic
//
always @(posedge clk `SC_FIFO_ASYNC_RESET)
if(!rst) wp <= #1 {aw{1'b0}};
else
if(clr) wp <= #1 {aw{1'b0}};
else
if(we) wp <= #1 wp_pl1;
assign wp_pl1 = wp + { {aw-1{1'b0}}, 1'b1};
assign wp_pl2 = wp + { {aw-2{1'b0}}, 2'b10};
always @(posedge clk `SC_FIFO_ASYNC_RESET)
if(!rst) rp <= #1 {aw{1'b0}};
else
if(clr) rp <= #1 {aw{1'b0}};
else
if(re) rp <= #1 rp_pl1;
assign rp_pl1 = rp + { {aw-1{1'b0}}, 1'b1};
////////////////////////////////////////////////////////////////////
//
// Combinatorial Full & Empty Flags
//
assign empty = ((wp == rp) & !gb);
assign full = ((wp == rp) & gb);
// Guard Bit ...
always @(posedge clk `SC_FIFO_ASYNC_RESET)
if(!rst) gb <= #1 1'b0;
else
if(clr) gb <= #1 1'b0;
else
if((wp_pl1 == rp) & we) gb <= #1 1'b1;
else
if(re) gb <= #1 1'b0;
////////////////////////////////////////////////////////////////////
//
// Registered Full & Empty Flags
//
// Guard Bit ...
always @(posedge clk `SC_FIFO_ASYNC_RESET)
if(!rst) gb2 <= #1 1'b0;
else
if(clr) gb2 <= #1 1'b0;
else
if((wp_pl2 == rp) & we) gb2 <= #1 1'b1;
else
if((wp != rp) & re) gb2 <= #1 1'b0;
always @(posedge clk `SC_FIFO_ASYNC_RESET)
if(!rst) full_r <= #1 1'b0;
else
if(clr) full_r <= #1 1'b0;
else
if(we & ((wp_pl1 == rp) & gb2) & !re) full_r <= #1 1'b1;
else
if(re & ((wp_pl1 != rp) | !gb2) & !we) full_r <= #1 1'b0;
always @(posedge clk `SC_FIFO_ASYNC_RESET)
if(!rst) empty_r <= #1 1'b1;
else
if(clr) empty_r <= #1 1'b1;
else
if(we & ((wp != rp_pl1) | gb2) & !re) empty_r <= #1 1'b0;
else
if(re & ((wp == rp_pl1) & !gb2) & !we) empty_r <= #1 1'b1;
////////////////////////////////////////////////////////////////////
//
// Combinatorial Full_n & Empty_n Flags
//
assign empty_n = cnt < n;
assign full_n = !(cnt < (max_size-n+1));
assign level = {2{cnt[aw]}} | cnt[aw-1:aw-2];
// N entries status
always @(posedge clk `SC_FIFO_ASYNC_RESET)
if(!rst) cnt <= #1 {aw+1{1'b0}};
else
if(clr) cnt <= #1 {aw+1{1'b0}};
else
if( re & !we) cnt <= #1 cnt + { {aw{1'b1}}, 1'b1};
else
if(!re & we) cnt <= #1 cnt + { {aw{1'b0}}, 1'b1};
////////////////////////////////////////////////////////////////////
//
// Registered Full_n & Empty_n Flags
//
always @(posedge clk `SC_FIFO_ASYNC_RESET)
if(!rst) empty_n_r <= #1 1'b1;
else
if(clr) empty_n_r <= #1 1'b1;
else
if(we & (cnt >= (n-1) ) & !re) empty_n_r <= #1 1'b0;
else
if(re & (cnt <= n ) & !we) empty_n_r <= #1 1'b1;
always @(posedge clk `SC_FIFO_ASYNC_RESET)
if(!rst) full_n_r <= #1 1'b0;
else
if(clr) full_n_r <= #1 1'b0;
else
if(we & (cnt >= (max_size-n) ) & !re) full_n_r <= #1 1'b1;
else
if(re & (cnt <= (max_size-n+1)) & !we) full_n_r <= #1 1'b0;
*/
endmodule
|