From a62861f3c91e88020d2c54e6500f431b9edde1d8 Mon Sep 17 00:00:00 2001 From: "Pavel V. Shatov (Meister)" Date: Sat, 1 Jul 2017 20:11:20 +0300 Subject: Added generic/vendor-specific primitive selector for simulation. --- src/rtl/modexpa7_factor.v | 9 +- src/rtl/pe/artix7/adder32_artix7.v | 97 ++++++++++++++++++ src/rtl/pe/artix7/dsp48e1_wrapper.v | 159 ++++++++++++++++++++++++++++++ src/rtl/pe/artix7/subtractor32_artix7.v | 95 ++++++++++++++++++ src/rtl/pe/generic/adder32_generic.v | 69 +++++++++++++ src/rtl/pe/generic/subtractor32_generic.v | 71 +++++++++++++ src/rtl/pe/modexpa7_pe_add.v | 27 +++-- src/rtl/pe/modexpa7_pe_settings.v | 13 +++ src/rtl/pe/modexpa7_pe_sub.v | 27 +++-- src/tb/tb_factor.v | 4 +- src/tb/tb_systolic_multiplier.v | 2 +- 11 files changed, 552 insertions(+), 21 deletions(-) create mode 100644 src/rtl/pe/artix7/adder32_artix7.v create mode 100644 src/rtl/pe/artix7/dsp48e1_wrapper.v create mode 100644 src/rtl/pe/artix7/subtractor32_artix7.v create mode 100644 src/rtl/pe/generic/adder32_generic.v create mode 100644 src/rtl/pe/generic/subtractor32_generic.v create mode 100644 src/rtl/pe/modexpa7_pe_settings.v (limited to 'src') diff --git a/src/rtl/modexpa7_factor.v b/src/rtl/modexpa7_factor.v index 7d8da72..b3ad130 100644 --- a/src/rtl/modexpa7_factor.v +++ b/src/rtl/modexpa7_factor.v @@ -276,14 +276,15 @@ module modexpa7_factor # /* mask borrow into the very first word */ sub_b_in_mask <= (fsm_next_state == FSM_STATE_CALC_3) ? 1'b1 : 1'b0; - ip_sub32 sub_inst + modexpa7_pe_sub sub_inst ( .clk (clk), + .ce (1'b1), .a (f1_data_in), .b (n_bram_out_dly), - .c_in (sub_b_in), - .s (sub_d), - .c_out (sub_b_out) + .b_in (sub_b_in), + .d (sub_d), + .b_out (sub_b_out) ); diff --git a/src/rtl/pe/artix7/adder32_artix7.v b/src/rtl/pe/artix7/adder32_artix7.v new file mode 100644 index 0000000..6da5bd9 --- /dev/null +++ b/src/rtl/pe/artix7/adder32_artix7.v @@ -0,0 +1,97 @@ +//------------------------------------------------------------------------------ +// +// adder32_artix7.v +// ----------------------------------------------------------------------------- +// Hardware (Artix-7 DSP48E1) 32-bit adder. +// +// Authors: Pavel Shatov +// +// Copyright (c) 2016-2017, NORDUnet A/S +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// - Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// - Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// +// - Neither the name of the NORDUnet nor the names of its contributors may be +// used to endorse or promote products derived from this software without +// specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +//------------------------------------------------------------------------------ + +module adder32_artix7 + ( + input clk, // clock + input ce, // clock enable + input [31: 0] a, // operand input + input [31: 0] b, // operand input + output [31: 0] s, // sum output + input c_in, // carry input + output c_out // carry output + ); + + // + // Lower and higher parts of operand + // + wire [17: 0] bl = b[17: 0]; + wire [13: 0] bh = b[31:18]; + + + // + // DSP48E1 Slice + // + + /* Operation Mode */ + wire [ 3: 0] dsp48e1_alumode = 4'b0000; + wire [ 6: 0] dsp48e1_opmode = 7'b0110011; + + /* Internal Product */ + wire [47: 0] p_int; + + dsp48e1_wrapper dsp_adder + ( + .clk (clk), + + .ce (ce), + + .carry (c_in), + + .alumode (dsp48e1_alumode), + .opmode (dsp48e1_opmode), + + .a ({{16{1'b0}}, bh}), + .b (bl), + .c ({{16{1'b0}}, a}), + + .p (p_int) + ); + + // + // Output Mapping + // + assign s = p_int[31: 0]; + assign c_out = p_int[32]; + + +endmodule + +//------------------------------------------------------------------------------ +// End-of-File +//------------------------------------------------------------------------------ diff --git a/src/rtl/pe/artix7/dsp48e1_wrapper.v b/src/rtl/pe/artix7/dsp48e1_wrapper.v new file mode 100644 index 0000000..11a21bc --- /dev/null +++ b/src/rtl/pe/artix7/dsp48e1_wrapper.v @@ -0,0 +1,159 @@ +//------------------------------------------------------------------------------ +// +// dsp48e1_wrapper.v +// ----------------------------------------------------------------------------- +// Hardware (Artix-7 DSP48E1) tile wrapper. +// +// Authors: Pavel Shatov +// +// Copyright (c) 2016, NORDUnet A/S +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// - Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// - Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// +// - Neither the name of the NORDUnet nor the names of its contributors may be +// used to endorse or promote products derived from this software without +// specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +//------------------------------------------------------------------------------ + +module dsp48e1_wrapper + ( + input clk, + + input ce, + + input [ 6: 0] opmode, + input [ 3: 0] alumode, + + input carry, + + input [29: 0] a, + input [17: 0] b, + input [47: 0] c, + + output [47: 0] p + ); + + + // + // Tile instantiation + // + DSP48E1 # + ( + .AREG (0), + .BREG (0), + .CREG (0), + .DREG (0), + .MREG (0), + .PREG (1), + .ADREG (0), + + .ACASCREG (0), + .BCASCREG (0), + .ALUMODEREG (0), + .INMODEREG (0), + .OPMODEREG (0), + .CARRYINREG (0), + .CARRYINSELREG (0), + + .A_INPUT ("DIRECT"), + .B_INPUT ("DIRECT"), + + .USE_DPORT ("FALSE"), + .USE_MULT ("DYNAMIC"), + .USE_SIMD ("ONE48"), + + .USE_PATTERN_DETECT ("NO_PATDET"), + .SEL_PATTERN ("PATTERN"), + .SEL_MASK ("MASK"), + .PATTERN (48'h000000000000), + .MASK (48'h3fffffffffff), + .AUTORESET_PATDET ("NO_RESET") + ) + DSP48E1_inst + ( + .CLK (clk), + + .RSTA (1'b0), + .RSTB (1'b0), + .RSTC (1'b0), + .RSTD (1'b0), + .RSTM (1'b0), + .RSTP (1'b0), + + .RSTCTRL (1'b0), + .RSTINMODE (1'b0), + .RSTALUMODE (1'b0), + .RSTALLCARRYIN (1'b0), + + .CEA1 (1'b0), + .CEA2 (1'b0), + .CEB1 (1'b0), + .CEB2 (1'b0), + .CEC (1'b0), + .CED (1'b0), + .CEM (1'b0), + .CEP (ce), + .CEAD (1'b0), + .CEALUMODE (1'b0), + .CEINMODE (1'b0), + + .CECTRL (1'b0), + .CECARRYIN (1'b0), + + .A (a), + .B (b), + .C (c), + .D ({25{1'b1}}), + .P (p), + + .CARRYIN (carry), + .CARRYOUT (), + .CARRYINSEL (3'b000), + + .CARRYCASCIN (1'b0), + .CARRYCASCOUT (), + + .PATTERNDETECT (), + .PATTERNBDETECT (), + + .OPMODE (opmode), + .ALUMODE (alumode), + .INMODE (5'b00000), + + .MULTSIGNIN (1'b0), + .MULTSIGNOUT (), + + .UNDERFLOW (), + .OVERFLOW (), + + .ACIN (30'd0), + .BCIN (18'd0), + .PCIN (48'd0), + + .ACOUT (), + .BCOUT (), + .PCOUT () + ); + +endmodule diff --git a/src/rtl/pe/artix7/subtractor32_artix7.v b/src/rtl/pe/artix7/subtractor32_artix7.v new file mode 100644 index 0000000..76e10c0 --- /dev/null +++ b/src/rtl/pe/artix7/subtractor32_artix7.v @@ -0,0 +1,95 @@ +//------------------------------------------------------------------------------ +// +// subtractor32_artix7.v +// ----------------------------------------------------------------------------- +// Hardware (Artix-7 DSP48E1) 32-bit subtractor. +// +// Authors: Pavel Shatov +// +// Copyright (c) 2016-2017, NORDUnet A/S +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// - Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// - Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// +// - Neither the name of the NORDUnet nor the names of its contributors may be +// used to endorse or promote products derived from this software without +// specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +//------------------------------------------------------------------------------ + +module subtractor32_artix7 + ( + input clk, + input ce, + input [31: 0] a, + input [31: 0] b, + output [31: 0] d, + input b_in, + output b_out + ); + + // + // Lower and higher parts of operand + // + wire [17: 0] bl = b[17: 0]; + wire [13: 0] bh = b[31:18]; + + // + // DSP48E1 Slice + // + + /* Operation Mode */ + wire [ 3: 0] dsp48e1_alumode = 4'b0011; + wire [ 6: 0] dsp48e1_opmode = 7'b0110011; + + /* Internal Product */ + wire [47: 0] p_int; + + dsp48e1_wrapper dsp_subtractor + ( + .clk (clk), + + .ce (ce), + + .carry (b_in), + + .alumode (dsp48e1_alumode), + .opmode (dsp48e1_opmode), + + .a ({{16{1'b0}}, bh}), + .b (bl), + .c ({{16{1'b0}}, a}), + + .p (p_int) + ); + + // + // Output Mapping + // + assign d = p_int[31: 0]; + assign b_out = p_int[32]; + +endmodule + +//------------------------------------------------------------------------------ +// End-of-File +//------------------------------------------------------------------------------ diff --git a/src/rtl/pe/generic/adder32_generic.v b/src/rtl/pe/generic/adder32_generic.v new file mode 100644 index 0000000..10ecfa4 --- /dev/null +++ b/src/rtl/pe/generic/adder32_generic.v @@ -0,0 +1,69 @@ +//------------------------------------------------------------------------------ +// +// adder32_generic.v +// ----------------------------------------------------------------------------- +// Generic 32-bit adder w/ clock enable. +// +// Authors: Pavel Shatov +// +// Copyright (c) 2016-2017, NORDUnet A/S +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// - Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// - Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// +// - Neither the name of the NORDUnet nor the names of its contributors may be +// used to endorse or promote products derived from this software without +// specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +//------------------------------------------------------------------------------ + +module adder32_generic + ( + input clk, // clock + input ce, // clock enable + input [31: 0] a, // operand input + input [31: 0] b, // operand input + output [31: 0] s, // sum output + input c_in, // carry input + output c_out // carry output + ); + + // + // Sum + // + reg [32: 0] s_int; + + always @(posedge clk) + if (ce) s_int <= {1'b0, a} + {1'b0, b} + {{32{1'b0}}, c_in}; + + // + // Output + // + assign s = s_int[31:0]; + assign c_out = s_int[32]; + + +endmodule + +//------------------------------------------------------------------------------ +// End-of-File +//------------------------------------------------------------------------------ diff --git a/src/rtl/pe/generic/subtractor32_generic.v b/src/rtl/pe/generic/subtractor32_generic.v new file mode 100644 index 0000000..3e78715 --- /dev/null +++ b/src/rtl/pe/generic/subtractor32_generic.v @@ -0,0 +1,71 @@ +//------------------------------------------------------------------------------ +// +// subtractor32_generic.v +// ----------------------------------------------------------------------------- +// Generic 32-bit subtractor w/ clock enable. +// +// Authors: Pavel Shatov +// +// Copyright (c) 2016-2017, NORDUnet A/S +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// - Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// - Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// +// - Neither the name of the NORDUnet nor the names of its contributors may be +// used to endorse or promote products derived from this software without +// specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +//------------------------------------------------------------------------------ + +module subtractor32_generic + ( + input clk, + input ce, + input [31: 0] a, + input [31: 0] b, + output [31: 0] d, + input b_in, + output b_out + ); + + + // + // Difference + // + reg [32: 0] d_int; + + always @(posedge clk) + if (ce) d_int <= {1'b0, a} - {1'b0, b} - {{32{1'b0}}, b_in}; + + + // + // Output + // + assign d = d_int[31:0]; + assign b_out = d_int[32]; + + +endmodule + +//------------------------------------------------------------------------------ +// End-of-File +//------------------------------------------------------------------------------ diff --git a/src/rtl/pe/modexpa7_pe_add.v b/src/rtl/pe/modexpa7_pe_add.v index 9cde591..467be5d 100644 --- a/src/rtl/pe/modexpa7_pe_add.v +++ b/src/rtl/pe/modexpa7_pe_add.v @@ -47,14 +47,27 @@ module modexpa7_pe_add output c_out ); - reg [32: 0] s_reg; - assign s = s_reg[31: 0]; - assign c_out = s_reg[32]; - - always @(posedge clk) - // - if (ce) s_reg <= {1'b0, a} + {1'b0, b} + {32'd0, c_in}; + // + // Include Primitive Selector + // + `include "modexpa7_pe_settings.v" + + + // + // Instantiate Vendor/Generic Primitive + // + `ADDER32_PRIMITIVE adder32_inst + ( + .clk(clk), + .ce(ce), + .a(a), + .b(b), + .s(s), + .c_in(c_in), + .c_out(c_out) + ); + endmodule diff --git a/src/rtl/pe/modexpa7_pe_settings.v b/src/rtl/pe/modexpa7_pe_settings.v new file mode 100644 index 0000000..97b5b89 --- /dev/null +++ b/src/rtl/pe/modexpa7_pe_settings.v @@ -0,0 +1,13 @@ +//`define USE_VENDOR_PRIMITIVES + +`ifdef USE_VENDOR_PRIMITIVES + +`define ADDER32_PRIMITIVE adder32_artix7 +`define SUBTRACTOR32_PRIMITIVE subtractor32_artix7 + +`else + +`define ADDER32_PRIMITIVE adder32_generic +`define SUBTRACTOR32_PRIMITIVE subtractor32_generic + +`endif diff --git a/src/rtl/pe/modexpa7_pe_sub.v b/src/rtl/pe/modexpa7_pe_sub.v index 85c5f65..2da4900 100644 --- a/src/rtl/pe/modexpa7_pe_sub.v +++ b/src/rtl/pe/modexpa7_pe_sub.v @@ -47,14 +47,27 @@ module modexpa7_pe_sub output b_out ); - reg [32: 0] d_reg; - assign d = d_reg[31: 0]; - assign b_out = d_reg[32]; - - always @(posedge clk) - // - if (ce) d_reg <= {1'b0, a} - {1'b0, b} - {32'd0, b_in}; + // + // Include Primitive Selector + // + `include "modexpa7_pe_settings.v" + + + // + // Instantiate Vendor/Generic Primitive + // + `SUBTRACTOR32_PRIMITIVE subtractor32_inst + ( + .clk(clk), + .ce(ce), + .a(a), + .b(b), + .d(d), + .b_in(b_in), + .b_out(b_out) + ); + endmodule diff --git a/src/tb/tb_factor.v b/src/tb/tb_factor.v index b53f7d8..d0e92dc 100644 --- a/src/tb/tb_factor.v +++ b/src/tb/tb_factor.v @@ -258,10 +258,10 @@ module tb_factor; tb_n_wren = 1; // start filling memories n_shreg = n; // preload shift register // - for (w=0; w