From d6092c84f08118c093142b7d8c6f9a332774400f Mon Sep 17 00:00:00 2001
From: "Pavel V. Shatov (Meister)" <meisterpaul1@yandex.ru>
Date: Fri, 11 Aug 2017 02:37:40 +0300
Subject: CRT mode seems to work. Finally.

Strangely enough non-CRT mode continues to work fine(!). One does not simply
add a feature without breaking something else. Very suspicious...
---
 src/tb/tb_exponentiator.v | 136 +++++++++++++++++++++++++++++++++++++++++++---
 1 file changed, 129 insertions(+), 7 deletions(-)

(limited to 'src/tb')

diff --git a/src/tb/tb_exponentiator.v b/src/tb/tb_exponentiator.v
index 440fedc..de801ac 100644
--- a/src/tb/tb_exponentiator.v
+++ b/src/tb/tb_exponentiator.v
@@ -212,12 +212,15 @@ module tb_exponentiator;
 		#100;
 
 			// test "honest" exponentiation
-//		test_exponent_384(M_384, D_384, FACTOR_384, N_384, N_COEFF_384, S_384);
-//		test_exponent_512(M_512, D_512, FACTOR_512, N_512, N_COEFF_512, S_512);
+		test_exponent_384(M_384, D_384, FACTOR_384, N_384, N_COEFF_384, S_384);
+		test_exponent_512(M_512, D_512, FACTOR_512, N_512, N_COEFF_512, S_512);
 
 			// test crt mode
-		test_exponent_192(M_384, DP_192, FACTOR_P_192, P_192, P_COEFF_192, MP_192);
-		//test_exponent_192(M_384, DQ_192, FACTOR_Q_192, Q_192, Q_COEFF_192, MQ_192);
+		test_exponent_192_crt(M_384, DP_192, FACTOR_P_192, P_192, P_COEFF_192, MP_192);
+		test_exponent_192_crt(M_384, DQ_192, FACTOR_Q_192, Q_192, Q_COEFF_192, MQ_192);
+
+		test_exponent_256_crt(M_512, DP_256, FACTOR_P_256, P_256, P_COEFF_256, MP_256);
+		test_exponent_256_crt(M_512, DQ_256, FACTOR_Q_256, Q_256, Q_COEFF_256, MQ_256);
 		
 	end
       
@@ -313,7 +316,7 @@ module tb_exponentiator;
 		//
 	endtask
 
-	task test_exponent_192;
+	task test_exponent_192_crt;
 		//
 		input	[383:0] m;
 		input	[191:0] d;
@@ -355,6 +358,50 @@ module tb_exponentiator;
 			//
 		end
 		//
+	endtask
+	
+	task test_exponent_256_crt;
+		//
+		input	[511:0] m;
+		input	[255:0] d;
+		input [255:0] f;
+		input	[255:0] n;
+		input	[255:0] n_coeff;
+		input	[255:0] s;
+		reg   [255:0] r;
+		//
+		integer i;
+		//
+		begin
+			//						
+			n_num_words = 4'd7;								// set number of words
+			d_num_bits = 9'd255;								// set number of bits
+			//
+			crt = 1;												// enable crt mode
+			//
+			write_memory_256(m, d, f, n, n_coeff);		// fill memory
+			
+			ena = 1;												// start operation
+			#10;													//
+			ena = 0;												// clear flag
+			
+			while (!rdy) #10;									// wait for operation to complete
+			read_memory_256(r);								// get result from memory
+						
+			$display("    calculated: %x", r);			// display result
+			$display("    expected:   %x", s);			//
+							
+				// check calculated value
+			if (r === s) begin
+				$display("        OK");
+				$display("SUCCESS: Test passed.");
+			end else begin
+				$display("        ERROR");
+				$display("FAILURE: Test not passed.");
+			end
+			//
+		end
+		//
 	endtask
 
 	//
@@ -516,6 +563,59 @@ module tb_exponentiator;
 	endtask
 
 
+		//
+		// write_memory_256
+		//
+	task write_memory_256;
+		//
+		input	[511:0] m;
+		input	[255:0] d;
+		input	[255:0] f;
+		input	[255:0] n;
+		input	[255:0] n_coeff;
+		reg	[511:0] m_shreg;
+		reg	[255:0] f_shreg;
+		reg	[255:0] d_shreg;
+		reg	[255:0] n_shreg;
+		reg	[255:0] n_coeff_shreg;
+		//
+		begin
+			//
+			tb_mdfn_wren	= 1;			// start filling memories
+			m_shreg			= m;			// preload shift register
+			d_shreg			= d;			// preload shift register
+			f_shreg			= f;			// preload shift register
+			n_shreg			= n;			// preload shift register
+			n_coeff_shreg	= n_coeff;	// preload shift register
+			//
+			for (w=0; w<NUM_WORDS_512; w=w+1) begin							// write all words
+				tb_mdfn_addr		= w[3:0];											// set address
+				tb_m_data			= m_shreg[31:0];									// set data
+				tb_d_data			= d_shreg[31:0];									// set data
+				tb_f_data			= f_shreg[31:0];									// set data
+				tb_n_data			= n_shreg[31:0];									// set data
+				tb_n_coeff_data	= n_coeff_shreg[31:0];							// set data
+				m_shreg				= {{32{1'bX}}, m_shreg[511:32]};				// update shift register
+				d_shreg				= {{32{1'bX}}, d_shreg[255:32]};				// update shift register
+				f_shreg				= {{32{1'bX}}, f_shreg[255:32]};				// update shift register
+				n_shreg				= {{32{1'bX}}, n_shreg[255:32]};				// update shift register
+				n_coeff_shreg		= {{32{1'bX}}, n_coeff_shreg[255:32]};		// update shift register
+				#10;																			// wait for 1 clock tick
+			end
+			//
+			tb_mdfn_addr		= {4{1'bX}};	// wipe addresses
+			tb_m_data			= {32{1'bX}};	// wipe data
+			tb_d_data			= {32{1'bX}};	// wipe data
+			tb_f_data			= {32{1'bX}};	// wipe data
+			tb_n_data			= {32{1'bX}};	// wipe data
+			tb_n_coeff_data	= {32{1'bX}};	// wipe data
+			tb_mdfn_wren	= 0;				// stop filling memory
+			//
+		end
+		//
+	endtask
+
+
 	//
 	// read_memory_384
 	//
@@ -584,8 +684,30 @@ module tb_exponentiator;
 			//
 		end
 		//
-	endtask
-
+	endtask
+	
+	//
+	// read_memory_256
+	//
+	task read_memory_256;
+		//
+		output	[255:0] r;
+		reg		[255:0] r_shreg;
+		//
+		begin
+			//
+			for (w=0; w<NUM_WORDS_512/2; w=w+1) begin		// read result word-by-word
+				tb_r_addr	= w[3:0];							// set address
+				#10;													// wait for 1 clock tick
+				r_shreg = {tb_r_data, r_shreg[255:32]};	// store data word
+			end
+			//
+			tb_r_addr = {4{1'bX}};								// wipe address
+			r = r_shreg;											// return
+			//
+		end
+		//
+	endtask
 
 endmodule
 
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