From 45b348b3a3c1ae8b355e73742af7c4897f1f5431 Mon Sep 17 00:00:00 2001 From: "Pavel V. Shatov (Meister)" Date: Mon, 4 Sep 2017 00:27:52 +0300 Subject: Cleaned up the core wrapper testbench. --- src/tb/tb_wrapper.v | 52 +++++++++++++++++++++------------------------------- 1 file changed, 21 insertions(+), 31 deletions(-) (limited to 'src/tb') diff --git a/src/tb/tb_wrapper.v b/src/tb/tb_wrapper.v index 054333e..c7619f0 100644 --- a/src/tb/tb_wrapper.v +++ b/src/tb/tb_wrapper.v @@ -71,6 +71,8 @@ module tb_wrapper; // rst_n = 1; // + // read common registers to make sure core header reads out ok + // read_reg('h00, tmp); // NAME0 read_reg('h01, tmp); // NAME1 read_reg('h02, tmp); // VERSION @@ -87,7 +89,7 @@ module tb_wrapper; write_reg('h10, 32'd0); // MODE read_reg ('h10, tmp); // - // pre-calculate 384-bit quantities + // fill in 384-bit modulus // shreg = N_384; for (i=0; i<384/32; i=i+1) begin @@ -95,9 +97,13 @@ module tb_wrapper; shreg = shreg >> 32; end // + // start precomputation + // write_reg('h08, 32'd0); // CONTROL.init = 0 write_reg('h08, 32'd1); // CONTROL.init = 1 // + // wait for precomputation to complete + // poll = 1; while (poll) begin #10; @@ -105,58 +111,39 @@ module tb_wrapper; poll = ~tmp[0]; // poll = STATUS.ready end // - // fill banks + // move modulus-dependent coefficient and Montgomery factor + // from "output" to "input" banks // for (i=0; i<384/32; i=i+1) begin - read_bank(3'b100, i[USE_OPERAND_ADDR_WIDTH-1:0], tmp); + read_bank (3'b100, i[USE_OPERAND_ADDR_WIDTH-1:0], tmp); write_bank(3'b101, i[USE_OPERAND_ADDR_WIDTH-1:0], tmp); - read_bank(3'b110, i[USE_OPERAND_ADDR_WIDTH-1:0], tmp); + read_bank (3'b110, i[USE_OPERAND_ADDR_WIDTH-1:0], tmp); write_bank(3'b111, i[USE_OPERAND_ADDR_WIDTH-1:0], tmp); end // + // fill in 384-bit message + // shreg = M_384; for (i=0; i<384/32; i=i+1) begin write_bank(3'b001, i[USE_OPERAND_ADDR_WIDTH-1:0], shreg[31:0]); shreg = shreg >> 32; end // + // fill in 384-bit exponent + // shreg = D_384; for (i=0; i<384/32; i=i+1) begin write_bank(3'b010, i[USE_OPERAND_ADDR_WIDTH-1:0], shreg[31:0]); shreg = shreg >> 32; end // - // wipe - // - shreg = {384{1'b0}}; - for (i=0; i<384/32; i=i+1) begin - write_bank(3'b000, i[USE_OPERAND_ADDR_WIDTH-1:0], shreg[31:0]); - shreg = shreg >> 32; - end - // - write_reg('h08, 32'd0); // CONTROL.init = 0 - write_reg('h08, 32'd1); // CONTROL.init = 1 - // - poll = 1; - while (poll) begin - #10; - read_reg('h09, tmp); // tmp = STATUS - poll = ~tmp[0]; // poll = STATUS.ready - end - // - // restore - // - shreg = N_384; - for (i=0; i<384/32; i=i+1) begin - write_bank(3'b000, i[USE_OPERAND_ADDR_WIDTH-1:0], shreg[31:0]); - shreg = shreg >> 32; - end - // - // + // start exponentiation // write_reg('h08, 32'd0); // CONTROL.next = 0 write_reg('h08, 32'd2); // CONTROL.next = 1 // + // wait for exponentiation to complete + // poll = 1; while (poll) begin #10; @@ -164,6 +151,8 @@ module tb_wrapper; poll = ~tmp[1]; // poll = STATUS.valid end // + // read result + // for (i=0; i<384/32; i=i+1) begin read_bank(3'b011, i[USE_OPERAND_ADDR_WIDTH-1:0], tmp); shreg = {tmp, shreg[383:32]}; @@ -228,5 +217,6 @@ module tb_wrapper; bus_addr = 'bX; end endtask + endmodule -- cgit v1.2.3