From f96ad01980fc4d0ed40f6ffb0fbb7c2006421c18 Mon Sep 17 00:00:00 2001
From: "Pavel V. Shatov (Meister)" <meisterpaul1@yandex.ru>
Date: Sun, 6 Aug 2017 21:46:35 +0300
Subject:  * Moved systolic processing element array into a separate module.  *
 Finished top-level wrapper module.

---
 src/tb/tb_wrapper.v | 123 +++++++++++++++++++++++++++++++++++++++-------------
 1 file changed, 94 insertions(+), 29 deletions(-)

(limited to 'src/tb/tb_wrapper.v')

diff --git a/src/tb/tb_wrapper.v b/src/tb/tb_wrapper.v
index bd8dbf1..fae0934 100644
--- a/src/tb/tb_wrapper.v
+++ b/src/tb/tb_wrapper.v
@@ -2,43 +2,108 @@
 
 module tb_wrapper;
 
-	// Inputs
+		/*
+		 * Settings
+		 */
+	localparam	USE_OPERAND_ADDR_WIDTH		= 7;
+	localparam	USE_SYSTOLIC_ARRAY_POWER	= 1;
+
+		/*
+		 * Clock (100 MHz)
+		 */
 	reg clk;
+	initial clk = 1'b0;
+	always #5 clk = ~clk;
+	
+		/*
+		 * Reset
+		 */
 	reg rst_n;
-	reg cs;
-	reg we;
-	reg [7:0] address;
-	reg [31:0] write_data;
-
-	// Outputs
-	wire [31:0] read_data;
+		 
+		 /*
+		  * Access Bus
+		  */
+	reg											bus_cs;
+	reg											bus_we;
+	reg	[USE_OPERAND_ADDR_WIDTH+2:0]	bus_addr;
+	reg	[                    32-1:0]	bus_wr_data;
+	wire	[                    32-1:0]	bus_rd_data;
 
-	// Instantiate the Unit Under Test (UUT)
-	modexpa7_wrapper uut (
-		.clk(clk), 
-		.rst_n(rst_n), 
-		.cs(cs), 
-		.we(we), 
-		.address(address), 
-		.write_data(write_data), 
-		.read_data(read_data)
+	modexpa7_wrapper #
+	(
+		.OPERAND_ADDR_WIDTH		(USE_OPERAND_ADDR_WIDTH),
+		.SYSTOLIC_ARRAY_POWER	(USE_SYSTOLIC_ARRAY_POWER)
+	)
+	uut
+	(
+		.clk			(clk),
+		
+		.rst_n		(rst_n),
+		
+		.cs			(bus_cs), 
+		.we			(bus_we), 
+		.address		(bus_addr), 
+		.write_data	(bus_wr_data), 
+		.read_data	(bus_rd_data)
 	);
 
+	reg	[31: 0]	tmp;
 	initial begin
-		// Initialize Inputs
-		clk = 0;
+		//
 		rst_n = 0;
-		cs = 0;
-		we = 0;
-		address = 0;
-		write_data = 0;
-
-		// Wait 100 ns for global reset to finish
-		#100;
-        
-		// Add stimulus here
-
+		//
+		bus_cs		= 0;
+		bus_we		= 0;
+		bus_addr		= 'bX;
+		bus_wr_data	= 'bX;
+		//
+		#200;
+		//
+		rst_n = 1;
+		//
+		read_reg('h00, tmp);			// NAME0
+		read_reg('h01, tmp);			// NAME1
+		read_reg('h02, tmp);			// VERSION
+		//
+		read_reg('h13, tmp);			// BUFFER_BITS
+		read_reg('h14, tmp);			// ARRAY_BITS
+		//
+		write_reg('h12, 32'd384);	// EXPONENT_BITS
+		read_reg ('h12, tmp);
+		//
+		write_reg('h11, 32'd384);	// MODULUS_BITS
+		read_reg ('h11, tmp);
+		//
+		//
 	end
+	
+	task read_reg;
+		input		[USE_OPERAND_ADDR_WIDTH+1:0]	addr;
+		output	[                    32-1:0]	data;
+		begin
+			bus_cs = 1;
+			bus_addr = {1'b0, addr};
+			#10;
+			bus_cs = 0;
+			bus_addr = 'bX;
+			data = bus_rd_data;
+		end
+	endtask
+
+	task write_reg;
+		input		[USE_OPERAND_ADDR_WIDTH+1:0]	addr;
+		input		[                    32-1:0]	data;
+		begin
+			bus_cs = 1;
+			bus_we = 1;
+			bus_addr = {1'b0, addr};
+			bus_wr_data = data;
+			#10;
+			bus_cs = 0;
+			bus_we = 0;
+			bus_addr = 'bX;
+		end
+	endtask
       
 endmodule
 
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