From a69a5308958c667e61cd90de51f64f9f4e0fcead Mon Sep 17 00:00:00 2001
From: "Pavel V. Shatov (Meister)" <meisterpaul1@yandex.ru>
Date: Sat, 1 Jul 2017 18:47:05 +0300
Subject: Added 512-bit test vector Cleaned up Verilog a bit

---
 src/tb/tb_factor.v | 228 +++++++++++++++++++++++++++++++++++++++++------------
 1 file changed, 178 insertions(+), 50 deletions(-)

(limited to 'src/tb/tb_factor.v')

diff --git a/src/tb/tb_factor.v b/src/tb/tb_factor.v
index 946883c..b53f7d8 100644
--- a/src/tb/tb_factor.v
+++ b/src/tb/tb_factor.v
@@ -49,6 +49,7 @@ module tb_factor;
 		// Parameters
 		//
 	localparam NUM_WORDS_384 = 384 / 32;
+	localparam NUM_WORDS_512 = 512 / 32;
 		
 		//
 		// Clock (100 MHz)
@@ -146,6 +147,7 @@ module tb_factor;
 		#100;
 		
 		test_factor_384(N_384);
+		test_factor_512(N_512);
 		
 	end
       
@@ -154,14 +156,16 @@ module tb_factor;
 		// Test Tasks
 		//
 		
-	task test_factor_384;
+	task test_factor_384;
+		//
 		input	[383:0] n;
 		reg	[383:0] f;
 		reg	[383:0] factor;
-		integer i;
+		integer i;
+		//
 		begin
-						
-			calc_factor_384(n, f);							// calculate factor on-the-fly
+			//			
+			calc_factor_384(n, f);	// calculate factor on-the-fly
 			
 				// make sure, that the value matches the one saved in the include file
 			if (f !== FACTOR_384) begin
@@ -170,8 +174,7 @@ module tb_factor;
 			end
 			
 			
-			n_num_words = 4'd11;								// set number of words
-			
+			n_num_words = 4'd11;								// set number of words
 			write_memory_384(n);								// fill memory
 			
 			ena = 1;												// start operation
@@ -180,8 +183,52 @@ module tb_factor;
 			
 			while (!rdy) #10;									// wait for operation to complete
 			read_memory_384(factor);						// get result from memory
+						
+			$display("    calculated: %x", factor);	// display result
+			$display("    expected:   %x", f);			//
 							
-			$display("    calculated: %x", factor);	//
+				// check calculated value
+			if (f === factor) begin
+				$display("        OK");
+				$display("SUCCESS: Test passed.");
+			end else begin
+				$display("        ERROR");
+				$display("FAILURE: Test not passed.");
+			end
+			//
+		end
+		//
+	endtask
+
+	task test_factor_512;
+		//
+		input	[511:0] n;
+		reg	[511:0] f;
+		reg	[511:0] factor;
+		integer i;
+		//
+		begin
+			//			
+			calc_factor_512(n, f);	// calculate factor on-the-fly
+			
+				// make sure, that the value matches the one saved in the include file
+			if (f !== FACTOR_512) begin
+				$display("ERROR: Calculated factor value differs from the one in the test vector!");
+				$finish;
+			end
+			
+			
+			n_num_words = 4'd15;								// set number of words
+			write_memory_512(n);								// fill memory
+			
+			ena = 1;												// start operation
+			#10;													//
+			ena = 0;												// clear flag
+			
+			while (!rdy) #10;									// wait for operation to complete
+			read_memory_512(factor);						// get result from memory
+						
+			$display("    calculated: %x", factor);	// display result
 			$display("    expected:   %x", f);			//
 							
 				// check calculated value
@@ -192,92 +239,173 @@ module tb_factor;
 				$display("        ERROR");
 				$display("FAILURE: Test not passed.");
 			end
-		
+			//
 		end
-	
+		//
 	endtask
 
 
+	//
+	// write_memory_384
+	//
 	task write_memory_384;
-
+		//
 		input	[383:0] n;
-
 		reg	[383:0] n_shreg;
-		
+		//
 		begin
+			//
+			tb_n_wren	= 1;	// start filling memories
+			n_shreg		= n;	// preload shift register
+			//
+			for (w=0; w<NUM_WORDS_512; w=w+1) begin				// write all words
+				tb_n_addr	= w[3:0];									// set address
+				tb_n_data	= n_shreg[31:0];							// set data
+				n_shreg		= {{32{1'bX}}, n_shreg[511:32]};		// update shift register
+				#10;															// wait for 1 clock tick
+			end
+			//
+			tb_n_addr	= {4{1'bX}};	// wipe addresses
+			tb_n_data	= {32{1'bX}};	// wipe data
+			tb_n_wren	= 0;				// stop filling memory
+			//
+		end
+		//
+	endtask
 			
-			tb_n_wren	= 1;														// start filling memories
-			
-			n_shreg       = n;													//
-			
-			for (w=0; w<NUM_WORDS_384; w=w+1) begin						// write all words
-				
-				tb_n_addr	= w[3:0];											// set addresses
-				
-				tb_n_data       = n_shreg[31:0];								//
-				
-				n_shreg       = {{32{1'bX}}, n_shreg[383:32]};			//
-				
-				#10;																	// wait for 1 clock tick
-				
+			
+	//
+	// write_memory_512
+	//
+	task write_memory_512;
+		//
+		input	[511:0] n;
+		reg	[511:0] n_shreg;
+		//
+		begin
+			//
+			tb_n_wren	= 1;	// start filling memories
+			n_shreg		= n;	// preload shift register
+			//
+			for (w=0; w<NUM_WORDS_512; w=w+1) begin				// write all words
+				tb_n_addr	= w[3:0];									// set address
+				tb_n_data	= n_shreg[31:0];							// set data
+				n_shreg		= {{32{1'bX}}, n_shreg[511:32]};		// update shift register
+				#10;															// wait for 1 clock tick
 			end
-			
-			tb_n_addr	= {4{1'bX}};											// wipe addresses
-			
-			tb_n_data       = {32{1'bX}};										//
-			
-			tb_n_wren = 0;														// stop filling memories
-		
+			//
+			tb_n_addr	= {4{1'bX}};	// wipe addresses
+			tb_n_data	= {32{1'bX}};	// wipe data
+			tb_n_wren	= 0;				// stop filling memory
+			//
 		end
-		
+		//
 	endtask
-			
 
+
+	//
+	// read_memory_384
+	//
 	task read_memory_384;
-	
+		//
 		output	[383:0] f;
 		reg		[383:0] f_shreg;
-		
+		//
 		begin
-		
-				// read result word-by-word
-			for (w=0; w<NUM_WORDS_384; w=w+1) begin
+			//
+			for (w=0; w<NUM_WORDS_384; w=w+1) begin		// read result word-by-word
 				tb_f_addr	= w[3:0];							// set address
 				#10;													// wait for 1 clock tick
 				f_shreg = {tb_f_data, f_shreg[383:32]};	// store data word
 			end
-			
+			//
 			tb_f_addr = {4{1'bX}};								// wipe address
 			f = f_shreg;											// return
-			
+			//
 		end
-		
+		//
 	endtask
 
 
-	task calc_factor_384;
+	//
+	// read_memory_512
+	//
+	task read_memory_512;
+		//
+		output	[511:0] f;
+		reg		[511:0] f_shreg;
+		//
+		begin
+			//
+			for (w=0; w<NUM_WORDS_512; w=w+1) begin		// read result word-by-word
+				tb_f_addr	= w[3:0];							// set address
+				#10;													// wait for 1 clock tick
+				f_shreg = {tb_f_data, f_shreg[511:32]};	// store data word
+			end
+			//
+			tb_f_addr = {4{1'bX}};								// wipe address
+			f = f_shreg;											// return
+			//
+		end
+		//
+	endtask
 
+
+	//
+	// calc_factor_384
+	//
+	task calc_factor_384;
+		//
 		input		[383:0] n;
 		output	[383:0] factor;
 		reg		[383:0] f;
 		reg		[384:0] f1;
 		reg		[384:0] f2;
 		integer i;
-
+		//
 		begin
-
+			//
 			f = 384'd1;
-
-			for (i=0; i<768; i=i+1) begin
+			//
+			for (i=0; i<2*384; i=i+1) begin
 				f1 = {f, 1'b0};
 				f2 = f1 - {1'b0, n};
 				f = (f1 >= {1'b0, n}) ? f2 : f1;
 			end
-
+			//
 			factor = f;
-
+			//
 		end
+		//
+	endtask
 
+
+	//
+	// calc_factor_512
+	//
+	task calc_factor_512;
+		//
+		input		[511:0] n;
+		output	[511:0] factor;
+		reg		[511:0] f;
+		reg		[512:0] f1;
+		reg		[512:0] f2;
+		integer i;
+		//
+		begin
+			//
+			f = 512'd1;
+			//
+			for (i=0; i<2*512; i=i+1) begin
+				f1 = {f, 1'b0};
+				f2 = f1 - {1'b0, n};
+				f = (f1 >= {1'b0, n}) ? f2 : f1;
+			end
+			//
+			factor = f;
+			//
+		end
+		//
 	endtask
 
 
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