From b33f595c014250072e9d787057293ef685eab5f3 Mon Sep 17 00:00:00 2001 From: "Pavel V. Shatov (Meister)" Date: Sun, 23 Jul 2017 04:10:47 +0300 Subject: Wrote top-level module. 4096-bit core with 16-tap systolic array synthesizes just fine: 10% slices 8% block memory 33% DSPs --- src/rtl/pe/modexpa7_primitive_switch.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/rtl/pe') diff --git a/src/rtl/pe/modexpa7_primitive_switch.v b/src/rtl/pe/modexpa7_primitive_switch.v index d38069b..3551d7a 100644 --- a/src/rtl/pe/modexpa7_primitive_switch.v +++ b/src/rtl/pe/modexpa7_primitive_switch.v @@ -1,4 +1,4 @@ -//`define USE_VENDOR_PRIMITIVES +`define USE_VENDOR_PRIMITIVES `ifdef USE_VENDOR_PRIMITIVES -- cgit v1.2.3