From caea5e361940c0d445a7d90446641a637c6d49cc Mon Sep 17 00:00:00 2001 From: "Pavel V. Shatov (Meister)" Date: Sat, 1 Jul 2017 22:26:32 +0300 Subject: Started porting generic multiplier to Xilinx primitives. --- src/rtl/pe/artix7/multiplier32_artix7.v | 83 +++++++++++++++++++++++++++++++++ 1 file changed, 83 insertions(+) create mode 100644 src/rtl/pe/artix7/multiplier32_artix7.v (limited to 'src/rtl/pe/artix7/multiplier32_artix7.v') diff --git a/src/rtl/pe/artix7/multiplier32_artix7.v b/src/rtl/pe/artix7/multiplier32_artix7.v new file mode 100644 index 0000000..5cc6340 --- /dev/null +++ b/src/rtl/pe/artix7/multiplier32_artix7.v @@ -0,0 +1,83 @@ +`timescale 1ns / 1ps + +module multiplier32_artix7 + ( + input clk, + input [31: 0] a, + input [31: 0] b, + input [31: 0] t, + input [31: 0] c_in, + output [31: 0] p, + output [31: 0] c_out + ); + + reg [31: 0] t_dly; + reg [31: 0] c_in_dly; + + always @(posedge clk) t_dly <= t; + always @(posedge clk) c_in_dly <= c_in; + + wire [31: 0] t_c_in_s; + wire t_c_in_c_out; + + reg t_c_in_c_out_dly; + + always @(posedge clk) t_c_in_c_out_dly <= t_c_in_c_out; + + adder32_artix7 add_t_c_in + ( + .clk (clk), + .a (t_dly), + .b (c_in_dly), + .c_in (1'b0), + .s (t_c_in_s), + .c_out (t_c_in_c_out) + ); + + wire [63: 0] a_b; + + wire [31: 0] a_b_lsb = a_b[31: 0]; + wire [31: 0] a_b_msb = a_b[63:32]; + + reg [31: 0] a_b_msb_dly; + + always @(posedge clk) a_b_msb_dly <= a_b_msb; + + ip_mul32 mul_a_b + ( + .clk (clk), + .a (a), + .b (b), + .p (a_b) + ); + + wire [31: 0] add_p_s; + wire add_p_c_out; + + reg [31: 0] add_p_s_dly; + + always @(posedge clk) add_p_s_dly <= add_p_s; + + assign p = add_p_s_dly; + + adder32_artix7 add_p + ( + .clk (clk), + .a (a_b_lsb), + .b (t_c_in_s), + .c_in (1'b0), + .s (add_p_s), + .c_out (add_p_c_out) + ); + + adder32_artix7 add_c_out + ( + .clk (clk), + .a (a_b_msb_dly), + .b ({{31{1'b0}}, t_c_in_c_out_dly}), + .c_in (add_p_c_out), + .s (c_out), + .c_out () + ); + +endmodule -- cgit v1.2.3