From a69a5308958c667e61cd90de51f64f9f4e0fcead Mon Sep 17 00:00:00 2001
From: "Pavel V. Shatov (Meister)" <meisterpaul1@yandex.ru>
Date: Sat, 1 Jul 2017 18:47:05 +0300
Subject: Added 512-bit test vector Cleaned up Verilog a bit

---
 src/rtl/modexpa7_n_coeff.v | 8 ++++++++
 1 file changed, 8 insertions(+)

(limited to 'src/rtl/modexpa7_n_coeff.v')

diff --git a/src/rtl/modexpa7_n_coeff.v b/src/rtl/modexpa7_n_coeff.v
index cba59e2..2bed5cd 100644
--- a/src/rtl/modexpa7_n_coeff.v
+++ b/src/rtl/modexpa7_n_coeff.v
@@ -145,6 +145,14 @@ module modexpa7_n_coeff #
 		//
 		// Cycle Counters
 		//
+		
+		/*
+		 * Maybe we can cheat and skip calculation of entire T every time.
+		 * During the first 32 cycles we only need the first word of T,
+		 * during the following 64 cycles the secord word, etc. Needs
+		 * further investigation...
+		 *
+		 */
 	reg	[OPERAND_ADDR_WIDTH+4:0]	cyc_cnt;
 		
 	wire	[OPERAND_ADDR_WIDTH+4:0]	cyc_cnt_zero = {{OPERAND_ADDR_WIDTH{1'b0}}, {5{1'b0}}};
-- 
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