From a69a5308958c667e61cd90de51f64f9f4e0fcead Mon Sep 17 00:00:00 2001
From: "Pavel V. Shatov (Meister)" <meisterpaul1@yandex.ru>
Date: Sat, 1 Jul 2017 18:47:05 +0300
Subject: Added 512-bit test vector Cleaned up Verilog a bit

---
 src/rtl/modexpa7_factor.v | 54 +++++++++++++++++++++++++++++++----------------
 1 file changed, 36 insertions(+), 18 deletions(-)

(limited to 'src/rtl/modexpa7_factor.v')

diff --git a/src/rtl/modexpa7_factor.v b/src/rtl/modexpa7_factor.v
index 510f7af..9fe3bfe 100644
--- a/src/rtl/modexpa7_factor.v
+++ b/src/rtl/modexpa7_factor.v
@@ -40,11 +40,11 @@ module modexpa7_factor #
 	(
 			//
 			// This sets the address widths of memory buffers. Internal data
-			// width is 32 bits, so for e.g. 1024-bit operands buffers must store
-			// 1024 / 32 = 32 words, and these need 5-bit address bus, because
-			// 2 ** 5 = 32.
+			// width is 32 bits, so for e.g. 2048-bit operands buffers must store
+			// 2048 / 32 = 64 words, and these need 6-bit address bus, because
+			// 2 ** 6 = 64.
 			//
-		parameter	OPERAND_ADDR_WIDTH = 5
+		parameter	OPERAND_ADDR_WIDTH = 6
 	)
 	(
 		input											clk,
@@ -63,6 +63,7 @@ module modexpa7_factor #
 
 		input		[OPERAND_ADDR_WIDTH-1:0]	n_num_words
 	);
+
 	
 		//
 		// FSM Declaration
@@ -89,6 +90,9 @@ module modexpa7_factor #
 	
 	localparam	[ 7: 0]	FSM_STATE_STOP		= 8'hFF;
 	
+		//
+		// FSM State / Next State
+		//
 	reg	[ 7: 0]	fsm_state = FSM_STATE_IDLE;
 	reg	[ 7: 0]	fsm_next_state;
 
@@ -97,20 +101,47 @@ module modexpa7_factor #
 		// Enable Delay (Trigger)
 		//
    reg ena_dly = 1'b0;
-   wire ena_trig = ena && !ena_dly;
+
+		/* delay enable by one clock cycle */
    always @(posedge clk) ena_dly <= ena;
+
+		/* trigger new operation when enable goes high */
+   wire ena_trig = ena && !ena_dly;
+	
 	
+		//
+		// Ready Flag Logic
+		//
+	reg rdy_reg = 1'b1;
+	assign rdy = rdy_reg;
+
+   always @(posedge clk or negedge rst_n)
+		
+			/* reset flag */
+		if (rst_n == 1'b0)						rdy_reg <= 1'b1;
+		else begin
+		
+				/* clear flag when operation is started */
+			if (fsm_state == FSM_STATE_IDLE)	rdy_reg <= ~ena_trig;
+			
+				/* set flag after operation is finished */
+			if (fsm_state == FSM_STATE_STOP)	rdy_reg <= 1'b1;			
+			
+		end
+
 		
 		//
 		// Parameters Latch
 		//
 	reg	[OPERAND_ADDR_WIDTH-1:0]	n_num_words_latch;
 
+		/* save number of words in modulus when new operation starts*/
 	always @(posedge clk)
 		//
 		if (fsm_next_state == FSM_STATE_INIT_1)
 			n_num_words_latch <= n_num_words;
 
+
 	
 		//
 		// Addresses
@@ -143,19 +174,6 @@ module modexpa7_factor #
 	
 	
 		
-		//
-		// Ready Flag Logic
-		//
-	reg rdy_reg = 1'b1;
-	assign rdy = rdy_reg;
-
-   always @(posedge clk or negedge rst_n)
-		//
-		if (rst_n == 1'b0)						rdy_reg <= 1'b1;
-		else begin
-			if (fsm_state == FSM_STATE_IDLE)	rdy_reg <= ~ena_trig;
-			if (fsm_state == FSM_STATE_STOP)	rdy_reg <= 1'b1;
-		end
 		
 		
 		//
-- 
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