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AgeCommit message (Collapse)Author
2017-07-01Added generic/vendor-specific primitive selector for simulation.Pavel V. Shatov (Meister)
2017-07-01Cleaned up Verilog sourcesPavel V. Shatov (Meister)
2017-07-01Added 512-bit test vectorPavel V. Shatov (Meister)
Cleaned up Verilog a bit
2017-07-01Finished modulus-dependent coefficient calculation module:Pavel V. Shatov (Meister)
* fixed bug with latency compensation * cleaned up Verilog source * added 512-bit testbench * works in simulator * synthesizes without warnings Changes: * made latency of generic processing element configurable
2017-06-27Added Montgomery modulus-dependent coefficient calculation blockPavel V. Shatov (Meister)
* work in progress
2017-06-27Added Montgomery factor calculation blockPavel V. Shatov (Meister)
* works in simulator * passes synthesis w/o warnings * code needs minor cleanup
2017-06-27Added systolic modular multiplier w/ testbench.Pavel V. Shatov (Meister)
* works in simulator * may have to change how internal operand buffer is pre-loaded (shift register instead of wide mux?) * code needs some cleanup
2017-06-27Added generic processing elements.Pavel V. Shatov (Meister)
2017-06-27Start conversion to systolic architecture.Pavel V. Shatov (Meister)
2016-06-14Initial commitPaul Selkirk