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2017-08-11Work in progress.Pavel V. Shatov (Meister)
2017-08-09Added 'modexpa7_' prefix to all the low-level modules in /src/rtl/pe/ to ↵Pavel V. Shatov (Meister)
prevent clashes with low-level modules in ECDSA multipliers. We should consolidate all the lowel-level stuff across all the math cores in the future.
2017-08-07 * Added readme filev0.20Pavel V. Shatov (Meister)
* Enabled vendor-specific primitive usage for compilation
2017-07-25Trying to fix the bug during calculation of SN in systolic multiplier.Pavel V. Shatov (Meister)
2017-07-23Wrote top-level module. 4096-bit core with 16-tap systolic array synthesizes ↵Pavel V. Shatov (Meister)
just fine: 10% slices 8% block memory 33% DSPs
2017-07-10 * made separate file for low-level settingsPavel V. Shatov (Meister)
* turned crazy triple multiplier array into one array with input mux
2017-07-04Fixed generic/vendor low-level primitives switch.Pavel V. Shatov (Meister)
2017-07-04Fixing generic/vendor primitive switching...Pavel V. Shatov (Meister)
2017-07-01Started porting generic multiplier to Xilinx primitives.Pavel V. Shatov (Meister)
2017-07-01Added generic/vendor-specific primitive selector for simulation.Pavel V. Shatov (Meister)
2017-07-01Finished modulus-dependent coefficient calculation module:Pavel V. Shatov (Meister)
* fixed bug with latency compensation * cleaned up Verilog source * added 512-bit testbench * works in simulator * synthesizes without warnings Changes: * made latency of generic processing element configurable
2017-06-27Added generic processing elements.Pavel V. Shatov (Meister)