| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2017-08-11 | Work in progress. | Pavel V. Shatov (Meister) | |
| 2017-08-09 | Added 'modexpa7_' prefix to all the low-level modules in /src/rtl/pe/ to ↵ | Pavel V. Shatov (Meister) | |
| prevent clashes with low-level modules in ECDSA multipliers. We should consolidate all the lowel-level stuff across all the math cores in the future. | |||
| 2017-08-07 | * Added readme filev0.20 | Pavel V. Shatov (Meister) | |
| * Enabled vendor-specific primitive usage for compilation | |||
| 2017-07-25 | Trying to fix the bug during calculation of SN in systolic multiplier. | Pavel V. Shatov (Meister) | |
| 2017-07-23 | Wrote top-level module. 4096-bit core with 16-tap systolic array synthesizes ↵ | Pavel V. Shatov (Meister) | |
| just fine: 10% slices 8% block memory 33% DSPs | |||
| 2017-07-10 | * made separate file for low-level settings | Pavel V. Shatov (Meister) | |
| * turned crazy triple multiplier array into one array with input mux | |||
| 2017-07-04 | Fixed generic/vendor low-level primitives switch. | Pavel V. Shatov (Meister) | |
| 2017-07-04 | Fixing generic/vendor primitive switching... | Pavel V. Shatov (Meister) | |
| 2017-07-01 | Started porting generic multiplier to Xilinx primitives. | Pavel V. Shatov (Meister) | |
| 2017-07-01 | Added generic/vendor-specific primitive selector for simulation. | Pavel V. Shatov (Meister) | |
| 2017-07-01 | Finished modulus-dependent coefficient calculation module: | Pavel V. Shatov (Meister) | |
| * fixed bug with latency compensation * cleaned up Verilog source * added 512-bit testbench * works in simulator * synthesizes without warnings Changes: * made latency of generic processing element configurable | |||
| 2017-06-27 | Added generic processing elements. | Pavel V. Shatov (Meister) | |
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index : core/math/modexpa7 | |
| Modular exponentiation using the Artix-7 FPGA | git repositories |
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