aboutsummaryrefslogtreecommitdiff
path: root/src/rtl/pe
AgeCommit message (Collapse)Author
2017-07-10 * made separate file for low-level settingsPavel V. Shatov (Meister)
* turned crazy triple multiplier array into one array with input mux
2017-07-04Fixed generic/vendor low-level primitives switch.Pavel V. Shatov (Meister)
2017-07-04Fixing generic/vendor primitive switching...Pavel V. Shatov (Meister)
2017-07-01Started porting generic multiplier to Xilinx primitives.Pavel V. Shatov (Meister)
2017-07-01Added generic/vendor-specific primitive selector for simulation.Pavel V. Shatov (Meister)
2017-07-01Finished modulus-dependent coefficient calculation module:Pavel V. Shatov (Meister)
* fixed bug with latency compensation * cleaned up Verilog source * added 512-bit testbench * works in simulator * synthesizes without warnings Changes: * made latency of generic processing element configurable
2017-06-27Added generic processing elements.Pavel V. Shatov (Meister)