| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2017-08-11 | CRT mode seems to work. Finally. | Pavel V. Shatov (Meister) | |
| Strangely enough non-CRT mode continues to work fine(!). One does not simply add a feature without breaking something else. Very suspicious... | |||
| 2017-08-06 | * Moved systolic processing element array into a separate module. | Pavel V. Shatov (Meister) | |
| * Finished top-level wrapper module. | |||
| 2017-07-25 | Trying to fix the bug during calculation of SN in systolic multiplier. | Pavel V. Shatov (Meister) | |
| 2017-07-24 | Started adding top-level wrapper. | Pavel V. Shatov (Meister) | |
| 2017-06-27 | Start conversion to systolic architecture. | Pavel V. Shatov (Meister) | |
| 2016-06-14 | Initial commit | Paul Selkirk | |
 |
index : core/math/modexpa7 | |
| Modular exponentiation using the Artix-7 FPGA | git repositories |
| aboutsummaryrefslogtreecommitdiff |