core/math/modexpa7 - Modular exponentiation using the Artix-7 FPGA

Age	Commit message (Collapse)	Author
2017-07-10	* made separate file for low-level settings	Pavel V. Shatov (Meister)
	* turned crazy triple multiplier array into one array with input mux
2017-07-04	Fixed generic/vendor low-level primitives switch.	Pavel V. Shatov (Meister)

2017-07-04	Fixing generic/vendor primitive switching...	Pavel V. Shatov (Meister)

2017-07-01	Started porting generic multiplier to Xilinx primitives.	Pavel V. Shatov (Meister)

2017-07-01	Added generic/vendor-specific primitive selector for simulation.	Pavel V. Shatov (Meister)

2017-07-01	Cleaned up Verilog sources	Pavel V. Shatov (Meister)

2017-07-01	Added 512-bit test vector	Pavel V. Shatov (Meister)
	Cleaned up Verilog a bit
2017-07-01	Finished modulus-dependent coefficient calculation module:	Pavel V. Shatov (Meister)
	* fixed bug with latency compensation * cleaned up Verilog source * added 512-bit testbench * works in simulator * synthesizes without warnings Changes: * made latency of generic processing element configurable
2017-06-27	Added test vectors, use scripts from the C model to (re-)generate them.	Pavel V. Shatov (Meister)

2017-06-27	Added Montgomery modulus-dependent coefficient calculation block	Pavel V. Shatov (Meister)
	* work in progress
2017-06-27	Added Montgomery factor calculation block	Pavel V. Shatov (Meister)
	* works in simulator * passes synthesis w/o warnings * code needs minor cleanup
2017-06-27	Added systolic modular multiplier w/ testbench.	Pavel V. Shatov (Meister)
	* works in simulator * may have to change how internal operand buffer is pre-loaded (shift register instead of wide mux?) * code needs some cleanup
2017-06-27	Added generic processing elements.	Pavel V. Shatov (Meister)

2017-06-27	Start conversion to systolic architecture.	Pavel V. Shatov (Meister)

2016-06-14	Initial commit	Paul Selkirk