| Age | Commit message (Expand) | Author |
|---|
| 2017-08-07 | * Added readme filev0.20 | Pavel V. Shatov (Meister) |
| 2017-08-06 | Added demo program that shows how to talk to the core and sign something. | Pavel V. Shatov (Meister) |
| 2017-08-06 | * Moved systolic processing element array into a separate module. | Pavel V. Shatov (Meister) |
| 2017-07-27 | Work in progress. | Pavel V. Shatov (Meister) |
| 2017-07-25 | Work in progress. | Pavel V. Shatov (Meister) |
| 2017-07-25 | Wide operand loader needs simplification... | Pavel V. Shatov (Meister) |
| 2017-07-25 | Trying to fix the bug during calculation of SN in systolic multiplier. | Pavel V. Shatov (Meister) |
| 2017-07-24 | Started adding top-level wrapper. | Pavel V. Shatov (Meister) |
| 2017-07-23 | Wrote top-level module. 4096-bit core with 16-tap systolic array synthesizes ... | Pavel V. Shatov (Meister) |
| 2017-07-23 | Converted pe_t array into a FIFO too. No more nasty messages during synthesis... | Pavel V. Shatov (Meister) |
| 2017-07-20 | Force inference of distributed memory for the simple FIFO used to store carries. | Pavel V. Shatov (Meister) |
| 2017-07-20 | Converted pe_c_out_mem two-dimensional array into a FIFO. | Pavel V. Shatov (Meister) |
| 2017-07-19 | Fixed bug in systolic multiplier (swapped indices), it only | Pavel V. Shatov (Meister) |
| 2017-07-19 | Added pre-multiplication step. | Pavel V. Shatov (Meister) |
| 2017-07-19 | Finished modular exponentiation module: | Pavel V. Shatov (Meister) |
| 2017-07-18 | Started adding exponentiator module w/ testbench. | Pavel V. Shatov (Meister) |
| 2017-07-13 | Systolic multiplier simplified a bit: | Pavel V. Shatov (Meister) |
| 2017-07-10 | * made separate file for low-level settings | Pavel V. Shatov (Meister) |
| 2017-07-04 | Fixed generic/vendor low-level primitives switch. | Pavel V. Shatov (Meister) |
| 2017-07-04 | Fixing generic/vendor primitive switching... | Pavel V. Shatov (Meister) |
| 2017-07-01 | Started porting generic multiplier to Xilinx primitives. | Pavel V. Shatov (Meister) |
| 2017-07-01 | Added generic/vendor-specific primitive selector for simulation. | Pavel V. Shatov (Meister) |
| 2017-07-01 | Cleaned up Verilog sources | Pavel V. Shatov (Meister) |
| 2017-07-01 | Added 512-bit test vector | Pavel V. Shatov (Meister) |
| 2017-07-01 | Finished modulus-dependent coefficient calculation module: | Pavel V. Shatov (Meister) |
| 2017-06-27 | Added test vectors, use scripts from the C model to (re-)generate them. | Pavel V. Shatov (Meister) |
| 2017-06-27 | Added Montgomery modulus-dependent coefficient calculation block | Pavel V. Shatov (Meister) |
| 2017-06-27 | Added Montgomery factor calculation block | Pavel V. Shatov (Meister) |
| 2017-06-27 | Added systolic modular multiplier w/ testbench. | Pavel V. Shatov (Meister) |
| 2017-06-27 | Added generic processing elements. | Pavel V. Shatov (Meister) |
| 2017-06-27 | Start conversion to systolic architecture. | Pavel V. Shatov (Meister) |
| 2016-06-14 | Initial commit | Paul Selkirk |
