1 files changed, 30 insertions, 10 deletions

diff --git a/src/rtl/modexpa7_top.v b/src/rtl/modexpa7_top.v
index 7723b88..ea3d2c2 100644
--- a/src/rtl/modexpa7_top.v
+++ b/src/rtl/modexpa7_top.v
@@ -109,24 +109,38 @@ module modexpa7_top #
 	reg valid_reg = 1'b0;
 	
 	assign ready = ready_reg;
-	assign valid = valid_reg;
+	assign valid = valid_reg;

+	

+	reg	init_trig_latch;

+	reg	next_trig_latch;

+	

+	always @(posedge clk)

+		//

+		if (fsm_state == FSM_STATE_IDLE)

+			//

+			case ({next_trig, init_trig})

+				2'b00:	{next_trig_latch, init_trig_latch} <= 2'b00;		// do nothing

+				2'b01:	{next_trig_latch, init_trig_latch} <= 2'b01;		// precalculate

+				2'b10:	{next_trig_latch, init_trig_latch} <= 2'b10;		// exponentiate

+				2'b11:	{next_trig_latch, init_trig_latch} <= 2'b01;		// 'init' has priority over 'next'

+			endcase
 
 		// ready flag logic
    always @(posedge clk or negedge rst_n)
 		//
-		if (rst_n == 1'b0)							ready_reg <= 1'b0;	// reset flag to default state
+		if (rst_n == 1'b0)									ready_reg <= 1'b0;	// reset flag to default state
 		else case (fsm_state)
-			FSM_STATE_IDLE:	if (init_trig)		ready_reg <= 1'b0;	// clear flag when operation is started
-			FSM_STATE_STOP:	if (!ready_reg)	ready_reg <= 1'b1;	// set flag after operation is finished
+			FSM_STATE_IDLE:	if (init_trig)				ready_reg <= 1'b0;	// clear flag when operation is started
+			FSM_STATE_STOP:	if (init_trig_latch)		ready_reg <= 1'b1;	// set flag after operation is finished
 		endcase
 
 		// valid flag logic
    always @(posedge clk or negedge rst_n)
 		//
-		if (rst_n == 1'b0)							valid_reg <= 1'b0;	// reset flag to default state
+		if (rst_n == 1'b0)									valid_reg <= 1'b0;	// reset flag to default state
 		else case (fsm_state)
-			FSM_STATE_IDLE:	if (next_trig)		valid_reg <= 1'b0;	// clear flag when operation is started
-			FSM_STATE_STOP:	if (!valid_reg)	valid_reg <= 1'b1;	// set flag after operation is finished
+			FSM_STATE_IDLE:	if (next_trig)				valid_reg <= 1'b0;	// clear flag when operation is started
+			FSM_STATE_STOP:	if (next_trig_latch)		valid_reg <= 1'b1;	// set flag after operation is finished
 		endcase
 
 	
@@ -137,14 +151,20 @@ module modexpa7_top #
 	reg	[OPERAND_ADDR_WIDTH+4:0]	exponent_num_bits_latch;
 
 		// save number of words in modulus when pre-calculation has been triggered,
-		// i.e. user has apparently loaded a new modulus into the core
+		// i.e. user has apparently loaded a new modulus into the core

+		//

+		// we also need to update modulus length when user wants to exponentiate,

+		// because he could have done precomputation for some modulus, then used

+		// a different length modulus and then reverted back the original modulus

+		// without doing precomputation (dammit, spent whole day chasing this bug :(
 	always @(posedge clk)
 		//
-		if (fsm_next_state == FSM_STATE_PRECALC_START)
+		if ((fsm_next_state == FSM_STATE_PRECALC_START) ||

+			 (fsm_next_state == FSM_STATE_EXPONENT_START))
 			modulus_num_words_latch <= modulus_num_words;
 
 		// save number of bits in exponent when exponentiation has been triggered,
-		// i.e. user has loaded a new message into the core and wants exponentiate
+		// i.e. user has loaded a new message into the core and wants to exponentiate
 	always @(posedge clk)
 		//
 		if (fsm_next_state == FSM_STATE_EXPONENT_START)