diff options
Diffstat (limited to 'src/rtl/pe')
| -rw-r--r-- | src/rtl/pe/modexpa7_pe_add.v | 63 | ||||
| -rw-r--r-- | src/rtl/pe/modexpa7_pe_mul.v | 83 | ||||
| -rw-r--r-- | src/rtl/pe/modexpa7_pe_sub.v | 63 |
3 files changed, 209 insertions, 0 deletions
diff --git a/src/rtl/pe/modexpa7_pe_add.v b/src/rtl/pe/modexpa7_pe_add.v new file mode 100644 index 0000000..9cde591 --- /dev/null +++ b/src/rtl/pe/modexpa7_pe_add.v @@ -0,0 +1,63 @@ +//======================================================================
+//
+// modexpa7_pe_add.v
+// -----------------------------------------------------------------------------
+// Low-level processing element (adder).
+//
+// Authors: Pavel Shatov
+//
+// Copyright (c) 2017, NORDUnet A/S All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+// - Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// - Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution.
+//
+// - Neither the name of the NORDUnet nor the names of its contributors may
+// be used to endorse or promote products derived from this software
+// without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
+// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
+// TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//======================================================================
+
+module modexpa7_pe_add
+ (
+ input clk,
+ input ce,
+ input [31: 0] a,
+ input [31: 0] b,
+ input c_in,
+ output [31: 0] s,
+ output c_out
+ );
+
+ reg [32: 0] s_reg;
+
+ assign s = s_reg[31: 0];
+ assign c_out = s_reg[32];
+
+ always @(posedge clk)
+ //
+ if (ce) s_reg <= {1'b0, a} + {1'b0, b} + {32'd0, c_in};
+
+endmodule
+
+//======================================================================
+// End of file
+//======================================================================
diff --git a/src/rtl/pe/modexpa7_pe_mul.v b/src/rtl/pe/modexpa7_pe_mul.v new file mode 100644 index 0000000..e56d152 --- /dev/null +++ b/src/rtl/pe/modexpa7_pe_mul.v @@ -0,0 +1,83 @@ +//======================================================================
+//
+// modexpa7_pe_mul.v
+// -----------------------------------------------------------------------------
+// Low-level processing element (multiplier).
+//
+// Authors: Pavel Shatov
+//
+// Copyright (c) 2017, NORDUnet A/S All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+// - Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// - Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution.
+//
+// - Neither the name of the NORDUnet nor the names of its contributors may
+// be used to endorse or promote products derived from this software
+// without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
+// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
+// TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//======================================================================
+
+module modexpa7_pe_mul
+ (
+ input clk,
+ input [31: 0] a,
+ input [31: 0] b,
+ input [31: 0] t,
+ input [31: 0] c_in,
+ output [31: 0] p,
+ output [31: 0] c_out
+ );
+
+ reg [31: 0] a_reg1;
+ reg [31: 0] b_reg1;
+ reg [31: 0] t_reg1;
+ reg [31: 0] t_reg2;
+ reg [31: 0] t_reg3;
+ reg [31: 0] c_reg1;
+ reg [31: 0] c_reg2;
+
+ reg [63: 0] ab_reg;
+ reg [63: 0] abc_reg;
+ reg [63: 0] abct_reg;
+
+ assign p = abct_reg[31: 0];
+ assign c_out = abct_reg[63:32];
+
+ always @(posedge clk) begin
+ a_reg1 <= a;
+ b_reg1 <= b;
+ c_reg1 <= c_in;
+ c_reg2 <= c_reg1;
+ t_reg1 <= t;
+ t_reg2 <= t_reg1;
+ t_reg3 <= t_reg2;
+
+ ab_reg <= {{32{1'b0}}, a_reg1} * {{32{1'b0}}, b_reg1};
+ abc_reg <= ab_reg + {{32{1'b0}}, c_reg2};
+ abct_reg <= abc_reg + {{32{1'b0}}, t_reg3};
+ end
+
+endmodule
+
+//======================================================================
+// End of file
+//======================================================================
diff --git a/src/rtl/pe/modexpa7_pe_sub.v b/src/rtl/pe/modexpa7_pe_sub.v new file mode 100644 index 0000000..85c5f65 --- /dev/null +++ b/src/rtl/pe/modexpa7_pe_sub.v @@ -0,0 +1,63 @@ +//======================================================================
+//
+// modexpa7_pe_sub.v
+// -----------------------------------------------------------------------------
+// Low-level processing element (subtractor).
+//
+// Authors: Pavel Shatov
+//
+// Copyright (c) 2017, NORDUnet A/S All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+// - Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// - Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution.
+//
+// - Neither the name of the NORDUnet nor the names of its contributors may
+// be used to endorse or promote products derived from this software
+// without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
+// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
+// TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//======================================================================
+
+module modexpa7_pe_sub
+ (
+ input clk,
+ input ce,
+ input [31: 0] a,
+ input [31: 0] b,
+ input b_in,
+ output [31: 0] d,
+ output b_out
+ );
+
+ reg [32: 0] d_reg;
+
+ assign d = d_reg[31: 0];
+ assign b_out = d_reg[32];
+
+ always @(posedge clk)
+ //
+ if (ce) d_reg <= {1'b0, a} - {1'b0, b} - {32'd0, b_in};
+
+endmodule
+
+//======================================================================
+// End of file
+//======================================================================
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