diff options
Diffstat (limited to 'src/rtl/modexpa7_systolic_multiplier.v')
| -rw-r--r-- | src/rtl/modexpa7_systolic_multiplier.v | 83 |
1 files changed, 71 insertions, 12 deletions
diff --git a/src/rtl/modexpa7_systolic_multiplier.v b/src/rtl/modexpa7_systolic_multiplier.v index 8cd28ff..382019c 100644 --- a/src/rtl/modexpa7_systolic_multiplier.v +++ b/src/rtl/modexpa7_systolic_multiplier.v @@ -600,7 +600,7 @@ module modexpa7_systolic_multiplier # reg [31: 0] pe_a [0:SYSTOLIC_ARRAY_LENGTH-1];
reg [31: 0] pe_b [0:SYSTOLIC_ARRAY_LENGTH-1];
reg [31: 0] pe_t [0:SYSTOLIC_ARRAY_LENGTH-1];
- reg [31: 0] pe_c_in [0:SYSTOLIC_ARRAY_LENGTH-1];
+ wire [31: 0] pe_c_in [0:SYSTOLIC_ARRAY_LENGTH-1];
wire [31: 0] pe_p [0:SYSTOLIC_ARRAY_LENGTH-1];
wire [31: 0] pe_c_out[0:SYSTOLIC_ARRAY_LENGTH-1];
@@ -608,9 +608,49 @@ module modexpa7_systolic_multiplier # //
// These can be turned into a FIFO (maybe later?)...
//
- reg [31: 0] pe_c_out_mem[0:SYSTOLIC_ARRAY_LENGTH-1][0:SYSTOLIC_NUM_CYCLES-1];
+ //reg [31: 0] pe_c_out_mem[0:SYSTOLIC_ARRAY_LENGTH-1][0:SYSTOLIC_NUM_CYCLES-1];
reg [31: 0] pe_t_mem [0:SYSTOLIC_ARRAY_LENGTH-1][0:SYSTOLIC_NUM_CYCLES-1];
+ reg fifo_c_rst;
+
+ wire fifo_c_wren;
+ wire fifo_c_rden;
+
+ wire debug_fifo_full;
+ wire debug_fifo_empty;
+
+ wire [32 * SYSTOLIC_ARRAY_LENGTH - 1 : 0] fifo_c_din;
+ wire [32 * SYSTOLIC_ARRAY_LENGTH - 1 : 0] fifo_c_dout;
+
+ /**/
+ modexpa7_simple_fifo #
+ (
+ .BUS_WIDTH (32 * SYSTOLIC_ARRAY_LENGTH),
+ .DEPTH_BITS (SYSTOLIC_CNTR_WIDTH)
+ )
+ fifo_c
+ (
+ .clk (clk),
+ .rst (fifo_c_rst),
+ .wr_en (fifo_c_wren),
+ .d_in (fifo_c_din),
+ .rd_en (fifo_c_rden),
+ .d_out (fifo_c_dout)
+ );
+ /**/
+ /*
+ ip_fifo_c fifo_c
+ (
+ .clk (clk),
+ .srst (fifo_c_rst),
+ .wr_en (fifo_c_wren),
+ .din (fifo_c_din),
+ .rd_en (fifo_c_rden),
+ .dout (fifo_c_dout),
+ .full (debug_fifo_full),
+ .empty (debug_fifo_empty)
+ );*/
+
generate for (i=0; i<SYSTOLIC_ARRAY_LENGTH; i=i+1)
begin : modexpa7_systolic_pe_multiplier
modexpa7_systolic_pe systolic_pe_inst
@@ -623,10 +663,13 @@ module modexpa7_systolic_multiplier # .p (pe_p[i]),
.c_out (pe_c_out[i])
);
+ assign pe_c_in[i] = fifo_c_dout[32 * (i + 1) - 1 -: 32];
+ assign fifo_c_din[32 * (i + 1) - 1 -: 32] = pe_c_out[i];
end
endgenerate
+
//
@@ -695,7 +738,23 @@ module modexpa7_systolic_multiplier # endcase
-
+ always @(posedge clk)
+ //
+ case (fsm_state)
+ FSM_STATE_MULT_A_B_START,
+ FSM_STATE_MULT_AB_N_COEFF_START,
+ FSM_STATE_MULT_Q_N_START: fifo_c_rst <= 1'b1;
+
+ FSM_STATE_MULT_A_B_CRUNCH,
+ FSM_STATE_MULT_AB_N_COEFF_CRUNCH,
+ FSM_STATE_MULT_Q_N_CRUNCH: if (shreg_done_load) fifo_c_rst <= 1'b0;
+ endcase
+
+
+ assign fifo_c_wren = shreg_now_unloading;
+ assign fifo_c_rden = shreg_now_loading;
+
+
always @(posedge clk) begin
@@ -835,9 +894,9 @@ module modexpa7_systolic_multiplier # FSM_STATE_MULT_AB_N_COEFF_CRUNCH,
FSM_STATE_MULT_Q_N_CRUNCH: begin
- if (shreg_now_unloading)
- for (j=0; j<SYSTOLIC_ARRAY_LENGTH; j=j+1)
- pe_c_out_mem[j][syst_cnt_unload] <= pe_c_out[j];
+ //if (shreg_now_unloading)
+ //for (j=0; j<SYSTOLIC_ARRAY_LENGTH; j=j+1)
+ //pe_c_out_mem[j][syst_cnt_unload] <= pe_c_out[j];
if (shreg_now_unloading) begin
@@ -867,12 +926,12 @@ module modexpa7_systolic_multiplier # pe_a[j] <= (ab_addr_ext > {1'b0, a_addr}) ? 32'd0 : a_bram_out;
pe_b[j] <= loader_dout[j];
pe_t[j] <= (a_addr == bram_addr_zero) ? 32'd0 : pe_t_mem[j][syst_cnt_load_dly];
- pe_c_in[j] <= (a_addr == bram_addr_zero) ? 32'd0 : pe_c_out_mem[j][syst_cnt_load_dly];
+ //pe_c_in[j] <= (a_addr == bram_addr_zero) ? 32'd0 : pe_c_out_mem[j][syst_cnt_load_dly];
end else begin
pe_a[j] <= 32'hXXXXXXXX;
pe_b[j] <= 32'hXXXXXXXX;
pe_t[j] <= 32'hXXXXXXXX;
- pe_c_in[j] <= 32'hXXXXXXXX;
+ //pe_c_in[j] <= 32'hXXXXXXXX;
end
//
if (fsm_state == FSM_STATE_MULT_AB_N_COEFF_CRUNCH)
@@ -883,12 +942,12 @@ module modexpa7_systolic_multiplier # pe_a[j] <= ab_data_out;
pe_b[j] <= loader_dout[j];
pe_t[j] <= (ab_addr_ext == bram_addr_ext_zero) ? 32'd0 : pe_t_mem[j][syst_cnt_load_dly];
- pe_c_in[j] <= (ab_addr_ext == bram_addr_ext_zero) ? 32'd0 : pe_c_out_mem[j][syst_cnt_load_dly];
+ //pe_c_in[j] <= (ab_addr_ext == bram_addr_ext_zero) ? 32'd0 : pe_c_out_mem[j][syst_cnt_load_dly];
end else begin
pe_a[j] <= 32'hXXXXXXXX;
pe_b[j] <= 32'hXXXXXXXX;
pe_t[j] <= 32'hXXXXXXXX;
- pe_c_in[j] <= 32'hXXXXXXXX;
+ //pe_c_in[j] <= 32'hXXXXXXXX;
end
//
if (fsm_state == FSM_STATE_MULT_Q_N_CRUNCH)
@@ -899,12 +958,12 @@ module modexpa7_systolic_multiplier # pe_a[j] <= (qn_addr_ext > {1'b0, q_addr}) ? 32'd0 : q_data_out;
pe_b[j] <= loader_dout[j];
pe_t[j] <= (q_addr == bram_addr_zero) ? 32'd0 : pe_t_mem[j][syst_cnt_load_dly];
- pe_c_in[j] <= (q_addr == bram_addr_zero) ? 32'd0 : pe_c_out_mem[j][syst_cnt_load_dly];
+ //pe_c_in[j] <= (q_addr == bram_addr_zero) ? 32'd0 : pe_c_out_mem[j][syst_cnt_load_dly];
end else begin
pe_a[j] <= 32'hXXXXXXXX;
pe_b[j] <= 32'hXXXXXXXX;
pe_t[j] <= 32'hXXXXXXXX;
- pe_c_in[j] <= 32'hXXXXXXXX;
+ //pe_c_in[j] <= 32'hXXXXXXXX;
end
//
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