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-rw-r--r--src/rtl/modexpa7_factor.v54
-rw-r--r--src/rtl/modexpa7_n_coeff.v8
-rw-r--r--src/tb/tb_factor.v228
3 files changed, 222 insertions, 68 deletions
diff --git a/src/rtl/modexpa7_factor.v b/src/rtl/modexpa7_factor.v
index 510f7af..9fe3bfe 100644
--- a/src/rtl/modexpa7_factor.v
+++ b/src/rtl/modexpa7_factor.v
@@ -40,11 +40,11 @@ module modexpa7_factor #
(
//
// This sets the address widths of memory buffers. Internal data
- // width is 32 bits, so for e.g. 1024-bit operands buffers must store
- // 1024 / 32 = 32 words, and these need 5-bit address bus, because
- // 2 ** 5 = 32.
+ // width is 32 bits, so for e.g. 2048-bit operands buffers must store
+ // 2048 / 32 = 64 words, and these need 6-bit address bus, because
+ // 2 ** 6 = 64.
//
- parameter OPERAND_ADDR_WIDTH = 5
+ parameter OPERAND_ADDR_WIDTH = 6
)
(
input clk,
@@ -63,6 +63,7 @@ module modexpa7_factor #
input [OPERAND_ADDR_WIDTH-1:0] n_num_words
);
+
//
// FSM Declaration
@@ -89,6 +90,9 @@ module modexpa7_factor #
localparam [ 7: 0] FSM_STATE_STOP = 8'hFF;
+ //
+ // FSM State / Next State
+ //
reg [ 7: 0] fsm_state = FSM_STATE_IDLE;
reg [ 7: 0] fsm_next_state;
@@ -97,20 +101,47 @@ module modexpa7_factor #
// Enable Delay (Trigger)
//
reg ena_dly = 1'b0;
- wire ena_trig = ena && !ena_dly;
+
+ /* delay enable by one clock cycle */
always @(posedge clk) ena_dly <= ena;
+
+ /* trigger new operation when enable goes high */
+ wire ena_trig = ena && !ena_dly;
+
+ //
+ // Ready Flag Logic
+ //
+ reg rdy_reg = 1'b1;
+ assign rdy = rdy_reg;
+
+ always @(posedge clk or negedge rst_n)
+
+ /* reset flag */
+ if (rst_n == 1'b0) rdy_reg <= 1'b1;
+ else begin
+
+ /* clear flag when operation is started */
+ if (fsm_state == FSM_STATE_IDLE) rdy_reg <= ~ena_trig;
+
+ /* set flag after operation is finished */
+ if (fsm_state == FSM_STATE_STOP) rdy_reg <= 1'b1;
+
+ end
+
//
// Parameters Latch
//
reg [OPERAND_ADDR_WIDTH-1:0] n_num_words_latch;
+ /* save number of words in modulus when new operation starts*/
always @(posedge clk)
//
if (fsm_next_state == FSM_STATE_INIT_1)
n_num_words_latch <= n_num_words;
+
//
// Addresses
@@ -143,19 +174,6 @@ module modexpa7_factor #
- //
- // Ready Flag Logic
- //
- reg rdy_reg = 1'b1;
- assign rdy = rdy_reg;
-
- always @(posedge clk or negedge rst_n)
- //
- if (rst_n == 1'b0) rdy_reg <= 1'b1;
- else begin
- if (fsm_state == FSM_STATE_IDLE) rdy_reg <= ~ena_trig;
- if (fsm_state == FSM_STATE_STOP) rdy_reg <= 1'b1;
- end
//
diff --git a/src/rtl/modexpa7_n_coeff.v b/src/rtl/modexpa7_n_coeff.v
index cba59e2..2bed5cd 100644
--- a/src/rtl/modexpa7_n_coeff.v
+++ b/src/rtl/modexpa7_n_coeff.v
@@ -145,6 +145,14 @@ module modexpa7_n_coeff #
//
// Cycle Counters
//
+
+ /*
+ * Maybe we can cheat and skip calculation of entire T every time.
+ * During the first 32 cycles we only need the first word of T,
+ * during the following 64 cycles the secord word, etc. Needs
+ * further investigation...
+ *
+ */
reg [OPERAND_ADDR_WIDTH+4:0] cyc_cnt;
wire [OPERAND_ADDR_WIDTH+4:0] cyc_cnt_zero = {{OPERAND_ADDR_WIDTH{1'b0}}, {5{1'b0}}};
diff --git a/src/tb/tb_factor.v b/src/tb/tb_factor.v
index 946883c..b53f7d8 100644
--- a/src/tb/tb_factor.v
+++ b/src/tb/tb_factor.v
@@ -49,6 +49,7 @@ module tb_factor;
// Parameters
//
localparam NUM_WORDS_384 = 384 / 32;
+ localparam NUM_WORDS_512 = 512 / 32;
//
// Clock (100 MHz)
@@ -146,6 +147,7 @@ module tb_factor;
#100;
test_factor_384(N_384);
+ test_factor_512(N_512);
end
@@ -154,14 +156,16 @@ module tb_factor;
// Test Tasks
//
- task test_factor_384;
+ task test_factor_384;
+ //
input [383:0] n;
reg [383:0] f;
reg [383:0] factor;
- integer i;
+ integer i;
+ //
begin
-
- calc_factor_384(n, f); // calculate factor on-the-fly
+ //
+ calc_factor_384(n, f); // calculate factor on-the-fly
// make sure, that the value matches the one saved in the include file
if (f !== FACTOR_384) begin
@@ -170,8 +174,7 @@ module tb_factor;
end
- n_num_words = 4'd11; // set number of words
-
+ n_num_words = 4'd11; // set number of words
write_memory_384(n); // fill memory
ena = 1; // start operation
@@ -180,8 +183,52 @@ module tb_factor;
while (!rdy) #10; // wait for operation to complete
read_memory_384(factor); // get result from memory
+
+ $display(" calculated: %x", factor); // display result
+ $display(" expected: %x", f); //
- $display(" calculated: %x", factor); //
+ // check calculated value
+ if (f === factor) begin
+ $display(" OK");
+ $display("SUCCESS: Test passed.");
+ end else begin
+ $display(" ERROR");
+ $display("FAILURE: Test not passed.");
+ end
+ //
+ end
+ //
+ endtask
+
+ task test_factor_512;
+ //
+ input [511:0] n;
+ reg [511:0] f;
+ reg [511:0] factor;
+ integer i;
+ //
+ begin
+ //
+ calc_factor_512(n, f); // calculate factor on-the-fly
+
+ // make sure, that the value matches the one saved in the include file
+ if (f !== FACTOR_512) begin
+ $display("ERROR: Calculated factor value differs from the one in the test vector!");
+ $finish;
+ end
+
+
+ n_num_words = 4'd15; // set number of words
+ write_memory_512(n); // fill memory
+
+ ena = 1; // start operation
+ #10; //
+ ena = 0; // clear flag
+
+ while (!rdy) #10; // wait for operation to complete
+ read_memory_512(factor); // get result from memory
+
+ $display(" calculated: %x", factor); // display result
$display(" expected: %x", f); //
// check calculated value
@@ -192,92 +239,173 @@ module tb_factor;
$display(" ERROR");
$display("FAILURE: Test not passed.");
end
-
+ //
end
-
+ //
endtask
+ //
+ // write_memory_384
+ //
task write_memory_384;
-
+ //
input [383:0] n;
-
reg [383:0] n_shreg;
-
+ //
begin
+ //
+ tb_n_wren = 1; // start filling memories
+ n_shreg = n; // preload shift register
+ //
+ for (w=0; w<NUM_WORDS_512; w=w+1) begin // write all words
+ tb_n_addr = w[3:0]; // set address
+ tb_n_data = n_shreg[31:0]; // set data
+ n_shreg = {{32{1'bX}}, n_shreg[511:32]}; // update shift register
+ #10; // wait for 1 clock tick
+ end
+ //
+ tb_n_addr = {4{1'bX}}; // wipe addresses
+ tb_n_data = {32{1'bX}}; // wipe data
+ tb_n_wren = 0; // stop filling memory
+ //
+ end
+ //
+ endtask
- tb_n_wren = 1; // start filling memories
-
- n_shreg = n; //
-
- for (w=0; w<NUM_WORDS_384; w=w+1) begin // write all words
-
- tb_n_addr = w[3:0]; // set addresses
-
- tb_n_data = n_shreg[31:0]; //
-
- n_shreg = {{32{1'bX}}, n_shreg[383:32]}; //
-
- #10; // wait for 1 clock tick
-
+
+ //
+ // write_memory_512
+ //
+ task write_memory_512;
+ //
+ input [511:0] n;
+ reg [511:0] n_shreg;
+ //
+ begin
+ //
+ tb_n_wren = 1; // start filling memories
+ n_shreg = n; // preload shift register
+ //
+ for (w=0; w<NUM_WORDS_512; w=w+1) begin // write all words
+ tb_n_addr = w[3:0]; // set address
+ tb_n_data = n_shreg[31:0]; // set data
+ n_shreg = {{32{1'bX}}, n_shreg[511:32]}; // update shift register
+ #10; // wait for 1 clock tick
end
-
- tb_n_addr = {4{1'bX}}; // wipe addresses
-
- tb_n_data = {32{1'bX}}; //
-
- tb_n_wren = 0; // stop filling memories
-
+ //
+ tb_n_addr = {4{1'bX}}; // wipe addresses
+ tb_n_data = {32{1'bX}}; // wipe data
+ tb_n_wren = 0; // stop filling memory
+ //
end
-
+ //
endtask
-
+
+ //
+ // read_memory_384
+ //
task read_memory_384;
-
+ //
output [383:0] f;
reg [383:0] f_shreg;
-
+ //
begin
-
- // read result word-by-word
- for (w=0; w<NUM_WORDS_384; w=w+1) begin
+ //
+ for (w=0; w<NUM_WORDS_384; w=w+1) begin // read result word-by-word
tb_f_addr = w[3:0]; // set address
#10; // wait for 1 clock tick
f_shreg = {tb_f_data, f_shreg[383:32]}; // store data word
end
-
+ //
tb_f_addr = {4{1'bX}}; // wipe address
f = f_shreg; // return
-
+ //
end
-
+ //
endtask
- task calc_factor_384;
+ //
+ // read_memory_512
+ //
+ task read_memory_512;
+ //
+ output [511:0] f;
+ reg [511:0] f_shreg;
+ //
+ begin
+ //
+ for (w=0; w<NUM_WORDS_512; w=w+1) begin // read result word-by-word
+ tb_f_addr = w[3:0]; // set address
+ #10; // wait for 1 clock tick
+ f_shreg = {tb_f_data, f_shreg[511:32]}; // store data word
+ end
+ //
+ tb_f_addr = {4{1'bX}}; // wipe address
+ f = f_shreg; // return
+ //
+ end
+ //
+ endtask
+
+ //
+ // calc_factor_384
+ //
+ task calc_factor_384;
+ //
input [383:0] n;
output [383:0] factor;
reg [383:0] f;
reg [384:0] f1;
reg [384:0] f2;
integer i;
-
+ //
begin
-
+ //
f = 384'd1;
-
- for (i=0; i<768; i=i+1) begin
+ //
+ for (i=0; i<2*384; i=i+1) begin
f1 = {f, 1'b0};
f2 = f1 - {1'b0, n};
f = (f1 >= {1'b0, n}) ? f2 : f1;
end
-
+ //
factor = f;
-
+ //
end
+ //
+ endtask
+
+ //
+ // calc_factor_512
+ //
+ task calc_factor_512;
+ //
+ input [511:0] n;
+ output [511:0] factor;
+ reg [511:0] f;
+ reg [512:0] f1;
+ reg [512:0] f2;
+ integer i;
+ //
+ begin
+ //
+ f = 512'd1;
+ //
+ for (i=0; i<2*512; i=i+1) begin
+ f1 = {f, 1'b0};
+ f2 = f1 - {1'b0, n};
+ f = (f1 >= {1'b0, n}) ? f2 : f1;
+ end
+ //
+ factor = f;
+ //
+ end
+ //
endtask
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