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-rw-r--r--src/rtl/modexpa7_factor.v11
-rw-r--r--src/rtl/modexpa7_n_coeff.v16
-rw-r--r--src/rtl/modexpa7_settings.vh (renamed from src/rtl/modexpa7_settings.v)12
-rw-r--r--src/rtl/modexpa7_systolic_multiplier.v8
-rw-r--r--src/rtl/modexpa7_systolic_multiplier_array.v6
-rw-r--r--src/rtl/pe/artix7/modexpa7_adder32_artix7.v97
-rw-r--r--src/rtl/pe/artix7/modexpa7_dsp48e1_wrapper.v159
-rw-r--r--src/rtl/pe/artix7/modexpa7_dsp48e1_wrapper_ext.v159
-rw-r--r--src/rtl/pe/artix7/modexpa7_multiplier32_artix7.v171
-rw-r--r--src/rtl/pe/artix7/modexpa7_subtractor32_artix7.v95
-rw-r--r--src/rtl/pe/artix7/modexpa7_systolic_pe_artix7.v126
-rw-r--r--src/rtl/pe/generic/modexpa7_adder32_generic.v69
-rw-r--r--src/rtl/pe/generic/modexpa7_subtractor32_generic.v71
-rw-r--r--src/rtl/pe/generic/modexpa7_systolic_pe_generic.v85
-rw-r--r--src/rtl/pe/modexpa7_adder32.v76
-rw-r--r--src/rtl/pe/modexpa7_primitive_switch.v16
-rw-r--r--src/rtl/pe/modexpa7_subtractor32.v76
-rw-r--r--src/rtl/pe/modexpa7_systolic_pe.v75
-rw-r--r--src/rtl/util/bram_1rw_1ro_readfirst.v88
-rw-r--r--src/rtl/util/bram_1rw_readfirst.v75
20 files changed, 31 insertions, 1460 deletions
diff --git a/src/rtl/modexpa7_factor.v b/src/rtl/modexpa7_factor.v
index 3f90e5d..cafe377 100644
--- a/src/rtl/modexpa7_factor.v
+++ b/src/rtl/modexpa7_factor.v
@@ -65,7 +65,13 @@ module modexpa7_factor #
);
- //
+ //
+ // Settings
+ //
+ `include "cryptech_primitive_switch.vh"
+
+
+ //
// FSM Declaration
//
localparam [ 7: 0] FSM_STATE_IDLE = 8'h00;
@@ -276,10 +282,9 @@ module modexpa7_factor #
/* mask borrow into the very first word */
sub_b_in_mask <= (fsm_next_state == FSM_STATE_CALC_3) ? 1'b1 : 1'b0;
- modexpa7_subtractor32 sub_inst
+ `CRYPTECH_PRIMITIVE_SUB32 sub_inst
(
.clk (clk),
- .ce (1'b1),
.a (f1_data_in),
.b (n_bram_out_dly),
.b_in (sub_b_in),
diff --git a/src/rtl/modexpa7_n_coeff.v b/src/rtl/modexpa7_n_coeff.v
index c2d7c9d..1ddb282 100644
--- a/src/rtl/modexpa7_n_coeff.v
+++ b/src/rtl/modexpa7_n_coeff.v
@@ -63,7 +63,13 @@ module modexpa7_n_coeff #
input [OPERAND_ADDR_WIDTH-1:0] n_num_words // number of words in modulus
);
-
+
+ //
+ // Settings
+ //
+ `include "cryptech_primitive_switch.vh"
+
+
//
// FSM Declaration
//
@@ -315,10 +321,9 @@ module modexpa7_n_coeff #
/* delay carry masking flag by one clock cycle (used later) */
always @(posedge clk) add1_c_in_mask_dly <= add1_c_in_mask;
- modexpa7_adder32 add1_inst
+ `CRYPTECH_PRIMITIVE_ADD32 add1_inst
(
.clk (clk), //
- .ce (1'b1), //
.a (~n_bram_out), // ~N
.b ({{31{1'b0}}, add1_b_lsb}), // 1
.c_in (add1_c_in), //
@@ -339,10 +344,9 @@ module modexpa7_n_coeff #
reg add2_c_in; // carry input
wire add2_c_out; // carry output
- modexpa7_adder32 add2_inst
+ `CRYPTECH_PRIMITIVE_ADD32 add2_inst
(
.clk (clk),
- .ce (1'b1),
.a (r_data_out),
.b (b_data_in),
.c_in (add2_c_in),
@@ -367,7 +371,7 @@ module modexpa7_n_coeff #
wire [31: 0] pe_p;
wire [31: 0] pe_c_out;
- modexpa7_systolic_pe pe_mul_inst
+ `CRYPTECH_PRIMITIVE_MODEXP_SYSTOLIC_PE pe_mul_inst
(
.clk (clk),
.a (pe_a),
diff --git a/src/rtl/modexpa7_settings.v b/src/rtl/modexpa7_settings.vh
index 0ec6978..aca24b4 100644
--- a/src/rtl/modexpa7_settings.v
+++ b/src/rtl/modexpa7_settings.vh
@@ -1,6 +1,6 @@
-localparam SYSTOLIC_PE_LATENCY = 4;
-
-localparam SYSTOLIC_CNTR_WIDTH = OPERAND_ADDR_WIDTH - SYSTOLIC_ARRAY_POWER;
-localparam SYSTOLIC_ARRAY_LENGTH = 2 ** SYSTOLIC_ARRAY_POWER;
-localparam SYSTOLIC_NUM_CYCLES = 2 ** SYSTOLIC_CNTR_WIDTH;
-
+localparam SYSTOLIC_PE_LATENCY = 4;
+
+localparam SYSTOLIC_CNTR_WIDTH = OPERAND_ADDR_WIDTH - SYSTOLIC_ARRAY_POWER;
+localparam SYSTOLIC_ARRAY_LENGTH = 2 ** SYSTOLIC_ARRAY_POWER;
+localparam SYSTOLIC_NUM_CYCLES = 2 ** SYSTOLIC_CNTR_WIDTH;
+
diff --git a/src/rtl/modexpa7_systolic_multiplier.v b/src/rtl/modexpa7_systolic_multiplier.v
index 40ccac8..a0f697a 100644
--- a/src/rtl/modexpa7_systolic_multiplier.v
+++ b/src/rtl/modexpa7_systolic_multiplier.v
@@ -81,8 +81,8 @@ module modexpa7_systolic_multiplier #
/*
* Include Settings
*/
- `include "pe/modexpa7_primitive_switch.v"
- `include "modexpa7_settings.v"
+ `include "cryptech_primitive_switch.vh"
+ `include "modexpa7_settings.vh"
/*
@@ -637,7 +637,7 @@ module modexpa7_systolic_multiplier #
reg add1_c_in_mask; // flag to not carry anything into the very first word
wire add1_c_out; // carry output
- modexpa7_adder32 add1_inst
+ `CRYPTECH_PRIMITIVE_ADD32_CE add1_inst
(
.clk (clk),
.ce (add1_ce),
@@ -659,7 +659,7 @@ module modexpa7_systolic_multiplier #
reg sub1_b_in_mask; // flag to not borrow anything from the very first word
wire sub1_b_out; // borrow output
- modexpa7_subtractor32 sub1_inst
+ `CRYPTECH_PRIMITIVE_SUB32_CE sub1_inst
(
.clk (clk),
.ce (sub1_ce),
diff --git a/src/rtl/modexpa7_systolic_multiplier_array.v b/src/rtl/modexpa7_systolic_multiplier_array.v
index de2a037..b6f9e32 100644
--- a/src/rtl/modexpa7_systolic_multiplier_array.v
+++ b/src/rtl/modexpa7_systolic_multiplier_array.v
@@ -69,8 +69,8 @@ module modexpa7_systolic_multiplier_array #
/*
* Include Settings
*/
- `include "pe/modexpa7_primitive_switch.v"
- `include "modexpa7_settings.v"
+ `include "cryptech_primitive_switch.vh"
+ `include "modexpa7_settings.vh"
/*
@@ -315,7 +315,7 @@ module modexpa7_systolic_multiplier_array #
//
begin : gen_modexpa7_systolic_pe
//
- modexpa7_systolic_pe systolic_pe_inst
+ `CRYPTECH_PRIMITIVE_MODEXP_SYSTOLIC_PE systolic_pe_inst
(
.clk (clk),
.a (pe_a[i]),
diff --git a/src/rtl/pe/artix7/modexpa7_adder32_artix7.v b/src/rtl/pe/artix7/modexpa7_adder32_artix7.v
deleted file mode 100644
index e0ff080..0000000
--- a/src/rtl/pe/artix7/modexpa7_adder32_artix7.v
+++ /dev/null
@@ -1,97 +0,0 @@
-//------------------------------------------------------------------------------
-//
-// modexpa7_adder32_artix7.v
-// -----------------------------------------------------------------------------
-// Hardware (Artix-7 DSP48E1) 32-bit adder.
-//
-// Authors: Pavel Shatov
-//
-// Copyright (c) 2016-2017, NORDUnet A/S
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions are met:
-//
-// - Redistributions of source code must retain the above copyright notice,
-// this list of conditions and the following disclaimer.
-//
-// - Redistributions in binary form must reproduce the above copyright notice,
-// this list of conditions and the following disclaimer in the documentation
-// and/or other materials provided with the distribution.
-//
-// - Neither the name of the NORDUnet nor the names of its contributors may be
-// used to endorse or promote products derived from this software without
-// specific prior written permission.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
-// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-// POSSIBILITY OF SUCH DAMAGE.
-//
-//------------------------------------------------------------------------------
-
-module modexpa7_adder32_artix7
- (
- input clk, // clock
- input ce, // clock enable
- input [31: 0] a, // operand input
- input [31: 0] b, // operand input
- output [31: 0] s, // sum output
- input c_in, // carry input
- output c_out // carry output
- );
-
- //
- // Lower and higher parts of operand
- //
- wire [17: 0] bl = b[17: 0];
- wire [13: 0] bh = b[31:18];
-
-
- //
- // DSP48E1 Slice
- //
-
- /* Operation Mode */
- wire [ 3: 0] dsp48e1_alumode = 4'b0000;
- wire [ 6: 0] dsp48e1_opmode = 7'b0110011;
-
- /* Internal Product */
- wire [47: 0] p_int;
-
- modexpa7_dsp48e1_wrapper dsp_adder
- (
- .clk (clk),
-
- .ce (ce),
-
- .carry (c_in),
-
- .alumode (dsp48e1_alumode),
- .opmode (dsp48e1_opmode),
-
- .a ({{16{1'b0}}, bh}),
- .b (bl),
- .c ({{16{1'b0}}, a}),
-
- .p (p_int)
- );
-
- //
- // Output Mapping
- //
- assign s = p_int[31: 0];
- assign c_out = p_int[32];
-
-
-endmodule
-
-//------------------------------------------------------------------------------
-// End-of-File
-//------------------------------------------------------------------------------
diff --git a/src/rtl/pe/artix7/modexpa7_dsp48e1_wrapper.v b/src/rtl/pe/artix7/modexpa7_dsp48e1_wrapper.v
deleted file mode 100644
index 1d6b721..0000000
--- a/src/rtl/pe/artix7/modexpa7_dsp48e1_wrapper.v
+++ /dev/null
@@ -1,159 +0,0 @@
-//------------------------------------------------------------------------------
-//
-// modexpa7_dsp48e1_wrapper.v
-// -----------------------------------------------------------------------------
-// Hardware (Artix-7 DSP48E1) tile wrapper.
-//
-// Authors: Pavel Shatov
-//
-// Copyright (c) 2016, NORDUnet A/S
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions are met:
-//
-// - Redistributions of source code must retain the above copyright notice,
-// this list of conditions and the following disclaimer.
-//
-// - Redistributions in binary form must reproduce the above copyright notice,
-// this list of conditions and the following disclaimer in the documentation
-// and/or other materials provided with the distribution.
-//
-// - Neither the name of the NORDUnet nor the names of its contributors may be
-// used to endorse or promote products derived from this software without
-// specific prior written permission.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
-// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-// POSSIBILITY OF SUCH DAMAGE.
-//
-//------------------------------------------------------------------------------
-
-module modexpa7_dsp48e1_wrapper
- (
- input clk,
-
- input ce,
-
- input [ 6: 0] opmode,
- input [ 3: 0] alumode,
-
- input carry,
-
- input [29: 0] a,
- input [17: 0] b,
- input [47: 0] c,
-
- output [47: 0] p
- );
-
-
- //
- // Tile instantiation
- //
- DSP48E1 #
- (
- .AREG (0),
- .BREG (0),
- .CREG (0),
- .DREG (0),
- .MREG (0),
- .PREG (1),
- .ADREG (0),
-
- .ACASCREG (0),
- .BCASCREG (0),
- .ALUMODEREG (0),
- .INMODEREG (0),
- .OPMODEREG (0),
- .CARRYINREG (0),
- .CARRYINSELREG (0),
-
- .A_INPUT ("DIRECT"),
- .B_INPUT ("DIRECT"),
-
- .USE_DPORT ("FALSE"),
- .USE_MULT ("DYNAMIC"),
- .USE_SIMD ("ONE48"),
-
- .USE_PATTERN_DETECT ("NO_PATDET"),
- .SEL_PATTERN ("PATTERN"),
- .SEL_MASK ("MASK"),
- .PATTERN (48'h000000000000),
- .MASK (48'h3fffffffffff),
- .AUTORESET_PATDET ("NO_RESET")
- )
- DSP48E1_inst
- (
- .CLK (clk),
-
- .RSTA (1'b0),
- .RSTB (1'b0),
- .RSTC (1'b0),
- .RSTD (1'b0),
- .RSTM (1'b0),
- .RSTP (1'b0),
-
- .RSTCTRL (1'b0),
- .RSTINMODE (1'b0),
- .RSTALUMODE (1'b0),
- .RSTALLCARRYIN (1'b0),
-
- .CEA1 (1'b0),
- .CEA2 (1'b0),
- .CEB1 (1'b0),
- .CEB2 (1'b0),
- .CEC (1'b0),
- .CED (1'b0),
- .CEM (1'b0),
- .CEP (ce),
- .CEAD (1'b0),
- .CEALUMODE (1'b0),
- .CEINMODE (1'b0),
-
- .CECTRL (1'b0),
- .CECARRYIN (1'b0),
-
- .A (a),
- .B (b),
- .C (c),
- .D ({25{1'b1}}),
- .P (p),
-
- .CARRYIN (carry),
- .CARRYOUT (),
- .CARRYINSEL (3'b000),
-
- .CARRYCASCIN (1'b0),
- .CARRYCASCOUT (),
-
- .PATTERNDETECT (),
- .PATTERNBDETECT (),
-
- .OPMODE (opmode),
- .ALUMODE (alumode),
- .INMODE (5'b00000),
-
- .MULTSIGNIN (1'b0),
- .MULTSIGNOUT (),
-
- .UNDERFLOW (),
- .OVERFLOW (),
-
- .ACIN (30'd0),
- .BCIN (18'd0),
- .PCIN (48'd0),
-
- .ACOUT (),
- .BCOUT (),
- .PCOUT ()
- );
-
-endmodule
diff --git a/src/rtl/pe/artix7/modexpa7_dsp48e1_wrapper_ext.v b/src/rtl/pe/artix7/modexpa7_dsp48e1_wrapper_ext.v
deleted file mode 100644
index bf0758c..0000000
--- a/src/rtl/pe/artix7/modexpa7_dsp48e1_wrapper_ext.v
+++ /dev/null
@@ -1,159 +0,0 @@
-//------------------------------------------------------------------------------
-//
-// modexpa7_dsp48e1_wrapper_ext.v
-// -----------------------------------------------------------------------------
-// Extended hardware (Artix-7 DSP48E1) tile wrapper.
-//
-// Authors: Pavel Shatov
-//
-// Copyright (c) 2016-2017, NORDUnet A/S
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions are met:
-//
-// - Redistributions of source code must retain the above copyright notice,
-// this list of conditions and the following disclaimer.
-//
-// - Redistributions in binary form must reproduce the above copyright notice,
-// this list of conditions and the following disclaimer in the documentation
-// and/or other materials provided with the distribution.
-//
-// - Neither the name of the NORDUnet nor the names of its contributors may be
-// used to endorse or promote products derived from this software without
-// specific prior written permission.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
-// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-// POSSIBILITY OF SUCH DAMAGE.
-//
-//------------------------------------------------------------------------------
-
-module modexpa7_dsp48e1_wrapper_ext #
- (
- parameter AREG = 1'b0,
- parameter PREG = 1'b0,
-
- parameter A_INPUT = "DIRECT"
- )
- (
- input clk,
- input [ 6: 0] opmode,
- input [29: 0] a,
- input [17: 0] b,
- output [47: 0] p,
- input [29: 0] acin,
- input [47: 0] pcin,
- output [29: 0] acout,
- output [47: 0] pcout
- );
-
- //
- // Tile instantiation
- //
- DSP48E1 #
- (
- .AREG (AREG),
- .BREG (1'b1),
- .CREG (0),
- .DREG (0),
- .MREG (0),
- .PREG (PREG),
- .ADREG (0),
-
- .ACASCREG (AREG),
- .BCASCREG (1'b1),
- .ALUMODEREG (0),
- .INMODEREG (0),
- .OPMODEREG (0),
- .CARRYINREG (0),
- .CARRYINSELREG (0),
-
- .A_INPUT (A_INPUT),
- .B_INPUT ("DIRECT"),
-
- .USE_DPORT ("FALSE"),
- .USE_MULT ("MULTIPLY"),
- .USE_SIMD ("ONE48"),
-
- .USE_PATTERN_DETECT ("NO_PATDET"),
- .SEL_PATTERN ("PATTERN"),
- .SEL_MASK ("MASK"),
- .PATTERN (48'h000000000000),
- .MASK (48'h3fffffffffff),
- .AUTORESET_PATDET ("NO_RESET")
- )
- DSP48E1_inst
- (
- .CLK (clk),
-
- .RSTA (1'b0),
- .RSTB (1'b0),
- .RSTC (1'b0),
- .RSTD (1'b0),
- .RSTM (1'b0),
- .RSTP (1'b0),
-
- .RSTCTRL (1'b0),
- .RSTINMODE (1'b0),
- .RSTALUMODE (1'b0),
- .RSTALLCARRYIN (1'b0),
-
- .CEA1 (1'b0),
- .CEA2 (AREG),
- .CEB1 (1'b0),
- .CEB2 (1'b1),
- .CEC (1'b0),
- .CED (1'b0),
- .CEM (1'b0),
- .CEP (PREG),
- .CEAD (1'b0),
- .CEALUMODE (1'b0),
- .CEINMODE (1'b0),
-
- .CECTRL (1'b0),
- .CECARRYIN (1'b0),
-
- .A (a),
- .B (b),
- .C ({48{1'b0}}),
- .D ({25{1'b1}}),
- .P (p),
-
- .CARRYIN (1'b0),
- .CARRYOUT (),
- .CARRYINSEL (3'b000),
-
- .CARRYCASCIN (1'b0),
- .CARRYCASCOUT (),
-
- .PATTERNDETECT (),
- .PATTERNBDETECT (),
-
- .OPMODE (opmode),
- .ALUMODE (4'b0000),
- .INMODE (5'b00000),
-
- .MULTSIGNIN (1'b0),
- .MULTSIGNOUT (),
-
- .UNDERFLOW (),
- .OVERFLOW (),
-
- .ACIN (acin),
- .BCIN (18'd0),
- .PCIN (pcin),
-
- .ACOUT (acout),
- .BCOUT (),
- .PCOUT (pcout)
- );
-
-endmodule
diff --git a/src/rtl/pe/artix7/modexpa7_multiplier32_artix7.v b/src/rtl/pe/artix7/modexpa7_multiplier32_artix7.v
deleted file mode 100644
index 40cdece..0000000
--- a/src/rtl/pe/artix7/modexpa7_multiplier32_artix7.v
+++ /dev/null
@@ -1,171 +0,0 @@
-//------------------------------------------------------------------------------
-//
-// modexpa7_multiplier32_artix7.v
-// -----------------------------------------------------------------------------
-// Hardware (Artix-7 DSP48E1) 32-bit multiplier.
-//
-// Authors: Pavel Shatov
-//
-// Copyright (c) 2016-2017, NORDUnet A/S
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions are met:
-//
-// - Redistributions of source code must retain the above copyright notice,
-// this list of conditions and the following disclaimer.
-//
-// - Redistributions in binary form must reproduce the above copyright notice,
-// this list of conditions and the following disclaimer in the documentation
-// and/or other materials provided with the distribution.
-//
-// - Neither the name of the NORDUnet nor the names of its contributors may be
-// used to endorse or promote products derived from this software without
-// specific prior written permission.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
-// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-// POSSIBILITY OF SUCH DAMAGE.
-//
-//------------------------------------------------------------------------------
-
-module modexpa7_multiplier32_artix7
- (
- input clk,
- input [31: 0] a,
- input [31: 0] b,
- output [63: 0] p
- );
-
- /* split a, b into smaller words */
- wire [16: 0] a_lo = a[16: 0];
- wire [16: 0] b_lo = b[16: 0];
- wire [14: 0] a_hi = a[31:17];
- wire [14: 0] b_hi = b[31:17];
-
- /* smaller sub-products */
- wire [47: 0] dsp1_p;
- wire [47: 0] dsp2_p;
- wire [47: 0] dsp4_p;
-
- /* direct output mapping */
- assign p[63:34] = dsp4_p[29: 0];
-
- /* delayed output mapping */
- genvar fd;
- generate for (fd=0; fd<17; fd=fd+1)
- begin : gen_FD
- FD # (.INIT( 1'b0)) FD_inst1 (.C(clk), .D(dsp1_p[fd]), .Q(p[fd + 0]));
- FD # (.INIT( 1'b0)) FD_inst3 (.C(clk), .D(dsp2_p[fd]), .Q(p[fd + 17]));
- end
- endgenerate
-
- /* product chains */
- wire [47: 0] dsp1_p_chain;
- wire [47: 0] dsp3_p_chain;
- wire [47: 0] dsp2_p_chain;
-
- /* operand chains */
- wire [29: 0] a_lo_chain;
- wire [29: 0] a_hi_chain;
-
- //
- // a_lo * b_lo
- //
- modexpa7_dsp48e1_wrapper_ext #
- (
- .AREG (1'b1),
- .PREG (1'b0),
- .A_INPUT ("DIRECT")
- )
- dsp1
- (
- .clk (clk),
- .opmode (7'b0110101),
- .a ({13'd0, a_lo}),
- .b ({1'b0, b_lo}),
- .p (dsp1_p),
- .acin (30'd0),
- .pcin (48'd0),
- .acout (a_lo_chain),
- .pcout (dsp1_p_chain)
- );
-
- //
- // a_hi * b_lo
- //
- modexpa7_dsp48e1_wrapper_ext #
- (
- .AREG (1'b1),
- .PREG (1'b0),
- .A_INPUT ("DIRECT")
- )
- dsp2
- (
- .clk (clk),
- .opmode (7'b0010101),
- .a ({15'd0, a_hi}),
- .b ({1'd0, b_lo}),
- .p (dsp2_p),
- .acin (30'd0),
- .pcin (dsp3_p_chain),
- .acout (a_hi_chain),
- .pcout (dsp2_p_chain)
- );
-
- //
- // a_lo * b_hi
- //
- modexpa7_dsp48e1_wrapper_ext #
- (
- .AREG (1'b0),
- .PREG (1'b0),
- .A_INPUT ("CASCADE")
- )
- dsp3
- (
- .clk (clk),
- .opmode (7'b1010101),
- .a (30'd0),
- .b ({3'd0, b_hi}),
- .p (),
- .acin (a_lo_chain),
- .pcin (dsp1_p_chain),
- .acout (),
- .pcout (dsp3_p_chain)
- );
-
- //
- // a_hi * b_hi
- //
- modexpa7_dsp48e1_wrapper_ext #
- (
- .AREG (1'b0),
- .PREG (1'b1),
- .A_INPUT ("CASCADE")
- )
- dsp4
- (
- .clk (clk),
- .opmode (7'b1010101),
- .a (30'd0),
- .b ({3'd0, b_hi}),
- .p (dsp4_p),
- .acin (a_hi_chain),
- .pcin (dsp2_p_chain),
- .acout (),
- .pcout ()
- );
-
-endmodule
-
-//------------------------------------------------------------------------------
-// End-of-File
-//------------------------------------------------------------------------------
diff --git a/src/rtl/pe/artix7/modexpa7_subtractor32_artix7.v b/src/rtl/pe/artix7/modexpa7_subtractor32_artix7.v
deleted file mode 100644
index 2241f24..0000000
--- a/src/rtl/pe/artix7/modexpa7_subtractor32_artix7.v
+++ /dev/null
@@ -1,95 +0,0 @@
-//------------------------------------------------------------------------------
-//
-// modexpa7_subtractor32_artix7.v
-// -----------------------------------------------------------------------------
-// Hardware (Artix-7 DSP48E1) 32-bit subtractor.
-//
-// Authors: Pavel Shatov
-//
-// Copyright (c) 2016-2017, NORDUnet A/S
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions are met:
-//
-// - Redistributions of source code must retain the above copyright notice,
-// this list of conditions and the following disclaimer.
-//
-// - Redistributions in binary form must reproduce the above copyright notice,
-// this list of conditions and the following disclaimer in the documentation
-// and/or other materials provided with the distribution.
-//
-// - Neither the name of the NORDUnet nor the names of its contributors may be
-// used to endorse or promote products derived from this software without
-// specific prior written permission.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
-// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-// POSSIBILITY OF SUCH DAMAGE.
-//
-//------------------------------------------------------------------------------
-
-module modexpa7_subtractor32_artix7
- (
- input clk,
- input ce,
- input [31: 0] a,
- input [31: 0] b,
- output [31: 0] d,
- input b_in,
- output b_out
- );
-
- //
- // Lower and higher parts of operand
- //
- wire [17: 0] bl = b[17: 0];
- wire [13: 0] bh = b[31:18];
-
- //
- // DSP48E1 Slice
- //
-
- /* Operation Mode */
- wire [ 3: 0] dsp48e1_alumode = 4'b0011;
- wire [ 6: 0] dsp48e1_opmode = 7'b0110011;
-
- /* Internal Product */
- wire [47: 0] p_int;
-
- modexpa7_dsp48e1_wrapper dsp_subtractor
- (
- .clk (clk),
-
- .ce (ce),
-
- .carry (b_in),
-
- .alumode (dsp48e1_alumode),
- .opmode (dsp48e1_opmode),
-
- .a ({{16{1'b0}}, bh}),
- .b (bl),
- .c ({{16{1'b0}}, a}),
-
- .p (p_int)
- );
-
- //
- // Output Mapping
- //
- assign d = p_int[31: 0];
- assign b_out = p_int[32];
-
-endmodule
-
-//------------------------------------------------------------------------------
-// End-of-File
-//------------------------------------------------------------------------------
diff --git a/src/rtl/pe/artix7/modexpa7_systolic_pe_artix7.v b/src/rtl/pe/artix7/modexpa7_systolic_pe_artix7.v
deleted file mode 100644
index 881e583..0000000
--- a/src/rtl/pe/artix7/modexpa7_systolic_pe_artix7.v
+++ /dev/null
@@ -1,126 +0,0 @@
-//------------------------------------------------------------------------------
-//
-// modexpa7_systolic_pe_artix7.v
-// -----------------------------------------------------------------------------
-// Hardware (Artix-7 DSP48E1) low-level systolic array processing element.
-//
-// Authors: Pavel Shatov
-//
-// Copyright (c) 2016-2017, NORDUnet A/S
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions are met:
-//
-// - Redistributions of source code must retain the above copyright notice,
-// this list of conditions and the following disclaimer.
-//
-// - Redistributions in binary form must reproduce the above copyright notice,
-// this list of conditions and the following disclaimer in the documentation
-// and/or other materials provided with the distribution.
-//
-// - Neither the name of the NORDUnet nor the names of its contributors may be
-// used to endorse or promote products derived from this software without
-// specific prior written permission.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
-// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-// POSSIBILITY OF SUCH DAMAGE.
-//
-//------------------------------------------------------------------------------
-
-module modexpa7_systolic_pe_artix7
- (
- input clk,
- input [31: 0] a,
- input [31: 0] b,
- input [31: 0] t,
- input [31: 0] c_in,
- output [31: 0] p,
- output [31: 0] c_out
- );
-
- reg [31: 0] t_dly;
- reg [31: 0] c_in_dly;
-
- always @(posedge clk) t_dly <= t;
- always @(posedge clk) c_in_dly <= c_in;
-
- wire [31: 0] t_c_in_s;
- wire t_c_in_c_out;
-
- reg t_c_in_c_out_dly;
-
- always @(posedge clk) t_c_in_c_out_dly <= t_c_in_c_out;
-
- modexpa7_adder32_artix7 add_t_c_in
- (
- .clk (clk),
- .ce (1'b1),
- .a (t_dly),
- .b (c_in_dly),
- .c_in (1'b0),
- .s (t_c_in_s),
- .c_out (t_c_in_c_out)
- );
-
- wire [63: 0] a_b;
-
- wire [31: 0] a_b_lsb = a_b[31: 0];
- wire [31: 0] a_b_msb = a_b[63:32];
-
- reg [31: 0] a_b_msb_dly;
-
- always @(posedge clk) a_b_msb_dly <= a_b_msb;
-
- modexpa7_multiplier32_artix7 mul_a_b
- (
- .clk (clk),
- .a (a),
- .b (b),
- .p (a_b)
- );
-
- wire [31: 0] add_p_s;
- wire add_p_c_out;
-
- reg [31: 0] add_p_s_dly;
-
- always @(posedge clk) add_p_s_dly <= add_p_s;
-
- assign p = add_p_s_dly;
-
- modexpa7_adder32_artix7 add_p
- (
- .clk (clk),
- .ce (1'b1),
- .a (a_b_lsb),
- .b (t_c_in_s),
- .c_in (1'b0),
- .s (add_p_s),
- .c_out (add_p_c_out)
- );
-
- modexpa7_adder32_artix7 add_c_out
- (
- .clk (clk),
- .ce (1'b1),
- .a (a_b_msb_dly),
- .b ({{31{1'b0}}, t_c_in_c_out_dly}),
- .c_in (add_p_c_out),
- .s (c_out),
- .c_out ()
- );
-
-endmodule
-
-//------------------------------------------------------------------------------
-// End-of-File
-//------------------------------------------------------------------------------
diff --git a/src/rtl/pe/generic/modexpa7_adder32_generic.v b/src/rtl/pe/generic/modexpa7_adder32_generic.v
deleted file mode 100644
index 8ecd292..0000000
--- a/src/rtl/pe/generic/modexpa7_adder32_generic.v
+++ /dev/null
@@ -1,69 +0,0 @@
-//------------------------------------------------------------------------------
-//
-// modexpa7_adder32_generic.v
-// -----------------------------------------------------------------------------
-// Generic 32-bit adder w/ clock enable.
-//
-// Authors: Pavel Shatov
-//
-// Copyright (c) 2016-2017, NORDUnet A/S
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions are met:
-//
-// - Redistributions of source code must retain the above copyright notice,
-// this list of conditions and the following disclaimer.
-//
-// - Redistributions in binary form must reproduce the above copyright notice,
-// this list of conditions and the following disclaimer in the documentation
-// and/or other materials provided with the distribution.
-//
-// - Neither the name of the NORDUnet nor the names of its contributors may be
-// used to endorse or promote products derived from this software without
-// specific prior written permission.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
-// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-// POSSIBILITY OF SUCH DAMAGE.
-//
-//------------------------------------------------------------------------------
-
-module modexpa7_adder32_generic
- (
- input clk, // clock
- input ce, // clock enable
- input [31: 0] a, // operand input
- input [31: 0] b, // operand input
- output [31: 0] s, // sum output
- input c_in, // carry input
- output c_out // carry output
- );
-
- //
- // Sum
- //
- reg [32: 0] s_int;
-
- always @(posedge clk)
- if (ce) s_int <= {1'b0, a} + {1'b0, b} + {{32{1'b0}}, c_in};
-
- //
- // Output
- //
- assign s = s_int[31:0];
- assign c_out = s_int[32];
-
-
-endmodule
-
-//------------------------------------------------------------------------------
-// End-of-File
-//------------------------------------------------------------------------------
diff --git a/src/rtl/pe/generic/modexpa7_subtractor32_generic.v b/src/rtl/pe/generic/modexpa7_subtractor32_generic.v
deleted file mode 100644
index b805c10..0000000
--- a/src/rtl/pe/generic/modexpa7_subtractor32_generic.v
+++ /dev/null
@@ -1,71 +0,0 @@
-//------------------------------------------------------------------------------
-//
-// modexpa7_subtractor32_generic.v
-// -----------------------------------------------------------------------------
-// Generic 32-bit subtractor w/ clock enable.
-//
-// Authors: Pavel Shatov
-//
-// Copyright (c) 2016-2017, NORDUnet A/S
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions are met:
-//
-// - Redistributions of source code must retain the above copyright notice,
-// this list of conditions and the following disclaimer.
-//
-// - Redistributions in binary form must reproduce the above copyright notice,
-// this list of conditions and the following disclaimer in the documentation
-// and/or other materials provided with the distribution.
-//
-// - Neither the name of the NORDUnet nor the names of its contributors may be
-// used to endorse or promote products derived from this software without
-// specific prior written permission.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
-// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-// POSSIBILITY OF SUCH DAMAGE.
-//
-//------------------------------------------------------------------------------
-
-module modexpa7_subtractor32_generic
- (
- input clk,
- input ce,
- input [31: 0] a,
- input [31: 0] b,
- output [31: 0] d,
- input b_in,
- output b_out
- );
-
-
- //
- // Difference
- //
- reg [32: 0] d_int;
-
- always @(posedge clk)
- if (ce) d_int <= {1'b0, a} - {1'b0, b} - {{32{1'b0}}, b_in};
-
-
- //
- // Output
- //
- assign d = d_int[31:0];
- assign b_out = d_int[32];
-
-
-endmodule
-
-//------------------------------------------------------------------------------
-// End-of-File
-//------------------------------------------------------------------------------
diff --git a/src/rtl/pe/generic/modexpa7_systolic_pe_generic.v b/src/rtl/pe/generic/modexpa7_systolic_pe_generic.v
deleted file mode 100644
index 389b1f9..0000000
--- a/src/rtl/pe/generic/modexpa7_systolic_pe_generic.v
+++ /dev/null
@@ -1,85 +0,0 @@
-//======================================================================
-//
-// modexpa7_systolic_pe_generic.v
-// -----------------------------------------------------------------------------
-// Generic low-level systolic array processing element.
-//
-// Authors: Pavel Shatov
-//
-// Copyright (c) 2017, NORDUnet A/S All rights reserved.
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions
-// are met:
-// - Redistributions of source code must retain the above copyright
-// notice, this list of conditions and the following disclaimer.
-//
-// - Redistributions in binary form must reproduce the above copyright
-// notice, this list of conditions and the following disclaimer in the
-// documentation and/or other materials provided with the distribution.
-//
-// - Neither the name of the NORDUnet nor the names of its contributors may
-// be used to endorse or promote products derived from this software
-// without specific prior written permission.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
-// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
-// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
-// TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-//
-//======================================================================
-
-module modexpa7_systolic_pe_generic
- (
- input clk,
- input [31: 0] a,
- input [31: 0] b,
- input [31: 0] t,
- input [31: 0] c_in,
- output [31: 0] p,
- output [31: 0] c_out
- );
-
- //
- // Customizable Latency
- //
- parameter LATENCY = 4;
-
- //
- // Delay Line
- //
- reg [63: 0] abct[1:LATENCY];
-
- //
- // Outputs
- //
- assign p = abct[LATENCY][31: 0];
- assign c_out = abct[LATENCY][63:32];
-
- //
- // Sub-products
- //
- wire [63: 0] ab = {{32{1'b0}}, a} * {{32{1'b0}}, b};
- wire [63: 0] ct = {{32{1'b0}}, c_in} + {{32{1'b0}}, t};
-
- //
- // Delay
- //
- integer i;
- always @(posedge clk)
- //
- for (i=1; i<=LATENCY; i=i+1)
- abct[i] <= (i == 1) ? ab + ct : abct[i-1];
-
-endmodule
-
-//======================================================================
-// End of file
-//======================================================================
diff --git a/src/rtl/pe/modexpa7_adder32.v b/src/rtl/pe/modexpa7_adder32.v
deleted file mode 100644
index 04f8a18..0000000
--- a/src/rtl/pe/modexpa7_adder32.v
+++ /dev/null
@@ -1,76 +0,0 @@
-//======================================================================
-//
-// modexpa7_adder32.v
-// -----------------------------------------------------------------------------
-// Low-level processing element wrapper (adder).
-//
-// Authors: Pavel Shatov
-//
-// Copyright (c) 2017, NORDUnet A/S All rights reserved.
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions
-// are met:
-// - Redistributions of source code must retain the above copyright
-// notice, this list of conditions and the following disclaimer.
-//
-// - Redistributions in binary form must reproduce the above copyright
-// notice, this list of conditions and the following disclaimer in the
-// documentation and/or other materials provided with the distribution.
-//
-// - Neither the name of the NORDUnet nor the names of its contributors may
-// be used to endorse or promote products derived from this software
-// without specific prior written permission.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
-// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
-// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
-// TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-//
-//======================================================================
-
-module modexpa7_adder32
- (
- input clk,
- input ce,
- input [31: 0] a,
- input [31: 0] b,
- input c_in,
- output [31: 0] s,
- output c_out
- );
-
-
- //
- // Include Primitive Selector
- //
- `include "modexpa7_primitive_switch.v"
-
-
- //
- // Instantiate Vendor/Generic Primitive
- //
- `ADDER32_PRIMITIVE adder32_inst
- (
- .clk(clk),
- .ce(ce),
- .a(a),
- .b(b),
- .s(s),
- .c_in(c_in),
- .c_out(c_out)
- );
-
-
-endmodule
-
-//======================================================================
-// End of file
-//======================================================================
diff --git a/src/rtl/pe/modexpa7_primitive_switch.v b/src/rtl/pe/modexpa7_primitive_switch.v
deleted file mode 100644
index fa958ec..0000000
--- a/src/rtl/pe/modexpa7_primitive_switch.v
+++ /dev/null
@@ -1,16 +0,0 @@
-`define USE_VENDOR_PRIMITIVES
-
-`ifdef USE_VENDOR_PRIMITIVES
-
-`define ADDER32_PRIMITIVE modexpa7_adder32_artix7
-`define SUBTRACTOR32_PRIMITIVE modexpa7_subtractor32_artix7
-`define SYSTOLIC_PE_PRIMITIVE modexpa7_systolic_pe_artix7
-
-`else
-
-`define ADDER32_PRIMITIVE modexpa7_adder32_generic
-`define SUBTRACTOR32_PRIMITIVE modexpa7_subtractor32_generic
-`define SYSTOLIC_PE_PRIMITIVE modexpa7_systolic_pe_generic
-
-
-`endif
diff --git a/src/rtl/pe/modexpa7_subtractor32.v b/src/rtl/pe/modexpa7_subtractor32.v
deleted file mode 100644
index a43d670..0000000
--- a/src/rtl/pe/modexpa7_subtractor32.v
+++ /dev/null
@@ -1,76 +0,0 @@
-//======================================================================
-//
-// modexpa7_subtractor32.v
-// -----------------------------------------------------------------------------
-// Low-level processing element wrapper (subtractor).
-//
-// Authors: Pavel Shatov
-//
-// Copyright (c) 2017, NORDUnet A/S All rights reserved.
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions
-// are met:
-// - Redistributions of source code must retain the above copyright
-// notice, this list of conditions and the following disclaimer.
-//
-// - Redistributions in binary form must reproduce the above copyright
-// notice, this list of conditions and the following disclaimer in the
-// documentation and/or other materials provided with the distribution.
-//
-// - Neither the name of the NORDUnet nor the names of its contributors may
-// be used to endorse or promote products derived from this software
-// without specific prior written permission.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
-// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
-// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
-// TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-//
-//======================================================================
-
-module modexpa7_subtractor32
- (
- input clk,
- input ce,
- input [31: 0] a,
- input [31: 0] b,
- input b_in,
- output [31: 0] d,
- output b_out
- );
-
-
- //
- // Include Primitive Selector
- //
- `include "modexpa7_primitive_switch.v"
-
-
- //
- // Instantiate Vendor/Generic Primitive
- //
- `SUBTRACTOR32_PRIMITIVE subtractor32_inst
- (
- .clk(clk),
- .ce(ce),
- .a(a),
- .b(b),
- .d(d),
- .b_in(b_in),
- .b_out(b_out)
- );
-
-
-endmodule
-
-//======================================================================
-// End of file
-//======================================================================
diff --git a/src/rtl/pe/modexpa7_systolic_pe.v b/src/rtl/pe/modexpa7_systolic_pe.v
deleted file mode 100644
index b284134..0000000
--- a/src/rtl/pe/modexpa7_systolic_pe.v
+++ /dev/null
@@ -1,75 +0,0 @@
-//======================================================================
-//
-// modexpa7_systolic_pe.v
-// -----------------------------------------------------------------------------
-// Low-level processing element wrapper (systolic array processing element).
-//
-// Authors: Pavel Shatov
-//
-// Copyright (c) 2017, NORDUnet A/S All rights reserved.
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions
-// are met:
-// - Redistributions of source code must retain the above copyright
-// notice, this list of conditions and the following disclaimer.
-//
-// - Redistributions in binary form must reproduce the above copyright
-// notice, this list of conditions and the following disclaimer in the
-// documentation and/or other materials provided with the distribution.
-//
-// - Neither the name of the NORDUnet nor the names of its contributors may
-// be used to endorse or promote products derived from this software
-// without specific prior written permission.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
-// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
-// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
-// TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-//
-//======================================================================
-
-module modexpa7_systolic_pe
- (
- input clk,
- input [31: 0] a,
- input [31: 0] b,
- input [31: 0] t,
- input [31: 0] c_in,
- output [31: 0] p,
- output [31: 0] c_out
- );
-
-
- //
- // Include Primitive Selector
- //
- `include "modexpa7_primitive_switch.v"
-
-
- //
- // Instantiate Vendor/Generic Primitive
- //
- `SYSTOLIC_PE_PRIMITIVE systolic_pe_inst
- (
- .clk(clk),
- .a(a),
- .b(b),
- .t(t),
- .c_in(c_in),
- .p(p),
- .c_out(c_out)
- );
-
-endmodule
-
-//======================================================================
-// End of file
-//======================================================================
diff --git a/src/rtl/util/bram_1rw_1ro_readfirst.v b/src/rtl/util/bram_1rw_1ro_readfirst.v
deleted file mode 100644
index 56cb24e..0000000
--- a/src/rtl/util/bram_1rw_1ro_readfirst.v
+++ /dev/null
@@ -1,88 +0,0 @@
-//======================================================================
-//
-// Copyright (c) 2015, 2017 NORDUnet A/S All rights reserved.
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions
-// are met:
-// - Redistributions of source code must retain the above copyright
-// notice, this list of conditions and the following disclaimer.
-//
-// - Redistributions in binary form must reproduce the above copyright
-// notice, this list of conditions and the following disclaimer in the
-// documentation and/or other materials provided with the distribution.
-//
-// - Neither the name of the NORDUnet nor the names of its contributors may
-// be used to endorse or promote products derived from this software
-// without specific prior written permission.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
-// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
-// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
-// TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-//
-//======================================================================
-
-`timescale 1ns / 1ps
-
-module bram_1rw_1ro_readfirst
- #(parameter MEM_WIDTH = 32,
- parameter MEM_ADDR_BITS = 8)
- (
- input wire clk,
-
- input wire [MEM_ADDR_BITS-1:0] a_addr,
- input wire a_wr,
- input wire [MEM_WIDTH-1:0] a_in,
- output wire [MEM_WIDTH-1:0] a_out,
-
- input wire [MEM_ADDR_BITS-1:0] b_addr,
- output wire [MEM_WIDTH-1:0] b_out
- );
-
-
- //
- // BRAM
- //
- (* RAM_STYLE="BLOCK" *)
- reg [MEM_WIDTH-1:0] bram[0:(2**MEM_ADDR_BITS)-1];
-
-
- //
- // Output Registers
- //
- reg [MEM_WIDTH-1:0] bram_reg_a;
- reg [MEM_WIDTH-1:0] bram_reg_b;
-
- assign a_out = bram_reg_a;
- assign b_out = bram_reg_b;
-
-
- //
- // Read-Write Port A
- //
- always @(posedge clk) begin
- //
- bram_reg_a <= bram[a_addr];
- //
- if (a_wr) bram[a_addr] <= a_in;
- //
- end
-
-
- //
- // Read-Only Port B
- //
- always @(posedge clk)
- //
- bram_reg_b <= bram[b_addr];
-
-
-endmodule
diff --git a/src/rtl/util/bram_1rw_readfirst.v b/src/rtl/util/bram_1rw_readfirst.v
deleted file mode 100644
index 30ecae8..0000000
--- a/src/rtl/util/bram_1rw_readfirst.v
+++ /dev/null
@@ -1,75 +0,0 @@
-//======================================================================
-//
-// Copyright (c) 2017, NORDUnet A/S All rights reserved.
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions
-// are met:
-// - Redistributions of source code must retain the above copyright
-// notice, this list of conditions and the following disclaimer.
-//
-// - Redistributions in binary form must reproduce the above copyright
-// notice, this list of conditions and the following disclaimer in the
-// documentation and/or other materials provided with the distribution.
-//
-// - Neither the name of the NORDUnet nor the names of its contributors may
-// be used to endorse or promote products derived from this software
-// without specific prior written permission.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
-// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
-// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
-// TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-//
-//======================================================================
-
-`timescale 1ns / 1ps
-
-module bram_1rw_readfirst
- #(parameter MEM_WIDTH = 32,
- parameter MEM_ADDR_BITS = 8)
- (
- input wire clk,
-
- input wire [MEM_ADDR_BITS-1:0] a_addr,
- input wire a_wr,
- input wire [MEM_WIDTH-1:0] a_in,
- output wire [MEM_WIDTH-1:0] a_out
- );
-
-
- //
- // BRAM
- //
- (* RAM_STYLE="BLOCK" *)
- reg [MEM_WIDTH-1:0] bram[0:(2**MEM_ADDR_BITS)-1];
-
-
- //
- // Output Register
- //
- reg [MEM_WIDTH-1:0] bram_reg_a;
-
- assign a_out = bram_reg_a;
-
-
- //
- // Read-Write Port A
- //
- always @(posedge clk) begin
- //
- bram_reg_a <= bram[a_addr];
- //
- if (a_wr) bram[a_addr] <= a_in;
- //
- end
-
-
-endmodule
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-23 01:01:43 +0000