diff options
| author | Pavel V. Shatov (Meister) <meisterpaul1@yandex.ru> | 2017-07-01 20:11:20 +0300 |
|---|---|---|
| committer | Pavel V. Shatov (Meister) <meisterpaul1@yandex.ru> | 2017-07-01 20:11:20 +0300 |
| commit | a62861f3c91e88020d2c54e6500f431b9edde1d8 (patch) | |
| tree | c9e9b1ff4790df8070bc6da0bb4e90f4a0cef134 /src/tb | |
| parent | 73fd79329a415514027abb976b76c890845aab0f (diff) | |
Added generic/vendor-specific primitive selector for simulation.
Diffstat (limited to 'src/tb')
| -rw-r--r-- | src/tb/tb_factor.v | 4 | ||||
| -rw-r--r-- | src/tb/tb_systolic_multiplier.v | 2 |
2 files changed, 3 insertions, 3 deletions
diff --git a/src/tb/tb_factor.v b/src/tb/tb_factor.v index b53f7d8..d0e92dc 100644 --- a/src/tb/tb_factor.v +++ b/src/tb/tb_factor.v @@ -258,10 +258,10 @@ module tb_factor; tb_n_wren = 1; // start filling memories n_shreg = n; // preload shift register
// - for (w=0; w<NUM_WORDS_512; w=w+1) begin // write all words + for (w=0; w<NUM_WORDS_384; w=w+1) begin // write all words tb_n_addr = w[3:0]; // set address tb_n_data = n_shreg[31:0]; // set data - n_shreg = {{32{1'bX}}, n_shreg[511:32]}; // update shift register + n_shreg = {{32{1'bX}}, n_shreg[383:32]}; // update shift register #10; // wait for 1 clock tick end // diff --git a/src/tb/tb_systolic_multiplier.v b/src/tb/tb_systolic_multiplier.v index a6380e5..21e319a 100644 --- a/src/tb/tb_systolic_multiplier.v +++ b/src/tb/tb_systolic_multiplier.v @@ -537,9 +537,9 @@ module tb_systolic_multiplier; endtask -
endmodule
+
//======================================================================
// End of file
//======================================================================
|