Added pre-multiplication step.

Added 512-bit testbench.

1 files changed, 95 insertions, 56 deletions

diff --git a/src/tb/tb_exponentiator.v b/src/tb/tb_exponentiator.v
index 3b612c5..c854e65 100644
--- a/src/tb/tb_exponentiator.v
+++ b/src/tb/tb_exponentiator.v
@@ -81,6 +81,7 @@ module tb_exponentiator;
 		//

 	wire	[ 3: 0]	core_m_addr;

 	wire	[ 3: 0]	core_d_addr;

+	wire	[ 3: 0]	core_f_addr;

 	wire	[ 3: 0]	core_n1_addr;

 	wire	[ 3: 0]	core_n2_addr;

 	wire	[ 3: 0]	core_n_coeff1_addr;

@@ -89,6 +90,7 @@ module tb_exponentiator;
 	

 	wire	[31: 0]	core_m_data;

 	wire	[31: 0]	core_d_data;

+	wire	[31: 0]	core_f_data;

 	wire	[31: 0]	core_n1_data;

 	wire	[31: 0]	core_n2_data;

 	wire	[31: 0]	core_n_coeff1_data;

@@ -97,48 +99,54 @@ module tb_exponentiator;
 

 	wire				core_r_wren;

 

-	reg	[ 3: 0]	tb_mdn_addr;
+	reg	[ 3: 0]	tb_mdfn_addr;
 	reg	[ 3: 0]	tb_r_addr;
 

 	reg	[31:0]	tb_m_data;
 	reg	[31:0]	tb_d_data;
+	reg	[31:0]	tb_f_data;
 	reg	[31:0]	tb_n_data;

 	reg	[31:0]	tb_n_coeff_data;
 	wire	[31:0]	tb_r_data;
 	
-	reg				tb_mdn_wren;
+	reg				tb_mdfn_wren;
 	

 		//

 		// BRAMs

 		//

 	bram_1rw_1ro_readfirst #(.MEM_WIDTH(32), .MEM_ADDR_BITS(4))
 	bram_m (.clk(clk),

-		.a_addr(tb_mdn_addr), .a_wr(tb_mdn_wren), .a_in(tb_m_data), .a_out(),
+		.a_addr(tb_mdfn_addr), .a_wr(tb_mdfn_wren), .a_in(tb_m_data), .a_out(),
 		.b_addr(core_m_addr), .b_out(core_m_data));
 

 	bram_1rw_1ro_readfirst #(.MEM_WIDTH(32), .MEM_ADDR_BITS(4))
 	bram_d (.clk(clk),

-		.a_addr(tb_mdn_addr), .a_wr(tb_mdn_wren), .a_in(tb_d_data), .a_out(),
+		.a_addr(tb_mdfn_addr), .a_wr(tb_mdfn_wren), .a_in(tb_d_data), .a_out(),
 		.b_addr(core_d_addr), .b_out(core_d_data));
 

 	bram_1rw_1ro_readfirst #(.MEM_WIDTH(32), .MEM_ADDR_BITS(4))
+	bram_f (.clk(clk),

+		.a_addr(tb_mdfn_addr), .a_wr(tb_mdfn_wren), .a_in(tb_f_data), .a_out(),
+		.b_addr(core_f_addr), .b_out(core_f_data));
+

+	bram_1rw_1ro_readfirst #(.MEM_WIDTH(32), .MEM_ADDR_BITS(4))
 	bram_n1 (.clk(clk),

-		.a_addr(tb_mdn_addr), .a_wr(tb_mdn_wren), .a_in(tb_n_data), .a_out(),
+		.a_addr(tb_mdfn_addr), .a_wr(tb_mdfn_wren), .a_in(tb_n_data), .a_out(),
 		.b_addr(core_n1_addr), .b_out(core_n1_data));
 

 	bram_1rw_1ro_readfirst #(.MEM_WIDTH(32), .MEM_ADDR_BITS(4))
 	bram_n2 (.clk(clk),

-		.a_addr(tb_mdn_addr), .a_wr(tb_mdn_wren), .a_in(tb_n_data), .a_out(),
+		.a_addr(tb_mdfn_addr), .a_wr(tb_mdfn_wren), .a_in(tb_n_data), .a_out(),
 		.b_addr(core_n2_addr), .b_out(core_n2_data));
 

 	bram_1rw_1ro_readfirst #(.MEM_WIDTH(32), .MEM_ADDR_BITS(4))
 	bram_n_coeff1 (.clk(clk),

-		.a_addr(tb_mdn_addr), .a_wr(tb_mdn_wren), .a_in(tb_n_coeff_data), .a_out(),
+		.a_addr(tb_mdfn_addr), .a_wr(tb_mdfn_wren), .a_in(tb_n_coeff_data), .a_out(),
 		.b_addr(core_n_coeff1_addr), .b_out(core_n_coeff1_data));

 

 	bram_1rw_1ro_readfirst #(.MEM_WIDTH(32), .MEM_ADDR_BITS(4))
 	bram_n_coeff2 (.clk(clk),

-		.a_addr(tb_mdn_addr), .a_wr(tb_mdn_wren), .a_in(tb_n_coeff_data), .a_out(),
+		.a_addr(tb_mdfn_addr), .a_wr(tb_mdfn_wren), .a_in(tb_n_coeff_data), .a_out(),
 		.b_addr(core_n_coeff2_addr), .b_out(core_n_coeff2_data));

 		
 	bram_1rw_1ro_readfirst #(.MEM_WIDTH(32), .MEM_ADDR_BITS(4))
@@ -164,6 +172,7 @@ module tb_exponentiator;
 		

 		.m_bram_addr			(core_m_addr),

 		.d_bram_addr			(core_d_addr),

+		.f_bram_addr			(core_f_addr),

 		.n1_bram_addr			(core_n1_addr),

 		.n2_bram_addr			(core_n2_addr),

 		.n_coeff1_bram_addr	(core_n_coeff1_addr),

@@ -172,6 +181,7 @@ module tb_exponentiator;
 

 		.m_bram_out				(core_m_data), 

 		.d_bram_out				(core_d_data), 

+		.f_bram_out				(core_f_data), 

 		.n1_bram_out			(core_n1_data), 

 		.n2_bram_out			(core_n2_data), 

 		.n_coeff1_bram_out	(core_n_coeff1_data), 

@@ -197,8 +207,8 @@ module tb_exponentiator;
 		rst_n = 1'b1;

 		#100;

 		

-		test_exponent_384(M_FACTOR_384, D_384, N_384, N_COEFF_384, S_384);

-		//test_exponent_512(M_512);

+		test_exponent_384(M_384, D_384, FACTOR_384, N_384, N_COEFF_384, S_384);

+		test_exponent_512(M_512, D_512, FACTOR_512, N_512, N_COEFF_512, S_512);

 		

 	end

       

@@ -211,6 +221,7 @@ module tb_exponentiator;
 		//
 		input	[383:0] m;

 		input	[383:0] d;

+		input [383:0] f;

 		input	[383:0] n;

 		input	[383:0] n_coeff;

 		input	[383:0] s;

@@ -223,7 +234,7 @@ module tb_exponentiator;
 			n_num_words = 4'd11;								// set number of words

 			d_num_bits = 9'd383;								// set number of bits

 			//

-			write_memory_384(m, d, n, n_coeff);			// fill memory

+			write_memory_384(m, d, f, n, n_coeff);		// fill memory

 			
 			ena = 1;												// start operation
 			#10;													//

@@ -247,40 +258,38 @@ module tb_exponentiator;
 		end
 		//

 	endtask
-	/*

-	task test_factor_512;

+

+	task test_exponent_512;

 		//
+		input	[511:0] m;

+		input	[511:0] d;

+		input [511:0] f;

 		input	[511:0] n;

-		reg	[511:0] f;

-		reg	[511:0] factor;

+		input	[511:0] n_coeff;

+		input	[511:0] s;

+		reg   [511:0] r;

+		//

 		integer i;

 		//
 		begin

-			//			

-			calc_factor_512(n, f);	// calculate factor on-the-fly

-			

-				// make sure, that the value matches the one saved in the include file

-			if (f !== FACTOR_512) begin

-				$display("ERROR: Calculated factor value differs from the one in the test vector!");

-				$finish;

-			end

-			

-			

+			//						

 			n_num_words = 4'd15;								// set number of words

-			write_memory_512(n);								// fill memory

+			d_num_bits = 9'd511;								// set number of bits

+			//

+			write_memory_512(m, d, f, n, n_coeff);		// fill memory

 			
 			ena = 1;												// start operation
 			#10;													//

 			ena = 0;												// clear flag

 			
 			while (!rdy) #10;									// wait for operation to complete

-			read_memory_512(factor);						// get result from memory
+			read_memory_512(r);								// get result from memory
 						

-			$display("    calculated: %x", factor);	// display result

-			$display("    expected:   %x", f);			//

+			$display("    calculated: %x", r);			// display result

+			$display("    expected:   %x", s);			//

 							

 				// check calculated value

-			if (f === factor) begin
+			if (r === s) begin
 				$display("        OK");

 				$display("SUCCESS: Test passed.");
 			end else begin

@@ -291,7 +300,7 @@ module tb_exponentiator;
 		end
 		//

 	endtask
-	*/

+

 

 	//

 	// write_memory_384

@@ -300,74 +309,104 @@ module tb_exponentiator;
 		//

 		input	[383:0] m;

 		input	[383:0] d;

+		input	[383:0] f;

 		input	[383:0] n;

 		input	[383:0] n_coeff;

 		reg	[383:0] m_shreg;

+		reg	[383:0] f_shreg;

 		reg	[383:0] d_shreg;

 		reg	[383:0] n_shreg;

 		reg	[383:0] n_coeff_shreg;

 		//

 		begin
 			//

-			tb_mdn_wren		= 1;			// start filling memories
+			tb_mdfn_wren	= 1;			// start filling memories
 			m_shreg			= m;			// preload shift register

 			d_shreg			= d;			// preload shift register

+			f_shreg			= f;			// preload shift register

 			n_shreg			= n;			// preload shift register

 			n_coeff_shreg	= n_coeff;	// preload shift register

 			//
 			for (w=0; w<NUM_WORDS_384; w=w+1) begin							// write all words
-				tb_mdn_addr			= w[3:0];											// set address
+				tb_mdfn_addr		= w[3:0];											// set address
 				tb_m_data			= m_shreg[31:0];									// set data
 				tb_d_data			= d_shreg[31:0];									// set data
+				tb_f_data			= f_shreg[31:0];									// set data
 				tb_n_data			= n_shreg[31:0];									// set data
 				tb_n_coeff_data	= n_coeff_shreg[31:0];							// set data
 				m_shreg				= {{32{1'bX}}, m_shreg[383:32]};				// update shift register
 				d_shreg				= {{32{1'bX}}, d_shreg[383:32]};				// update shift register
+				f_shreg				= {{32{1'bX}}, f_shreg[383:32]};				// update shift register
 				n_shreg				= {{32{1'bX}}, n_shreg[383:32]};				// update shift register
 				n_coeff_shreg		= {{32{1'bX}}, n_coeff_shreg[383:32]};		// update shift register
 				#10;																			// wait for 1 clock tick
 			end
 			//
-			tb_mdn_addr			= {4{1'bX}};	// wipe addresses
+			tb_mdfn_addr		= {4{1'bX}};	// wipe addresses
 			tb_m_data			= {32{1'bX}};	// wipe data
 			tb_d_data			= {32{1'bX}};	// wipe data
+			tb_f_data			= {32{1'bX}};	// wipe data
 			tb_n_data			= {32{1'bX}};	// wipe data
 			tb_n_coeff_data	= {32{1'bX}};	// wipe data
-			tb_mdn_wren	= 0;				// stop filling memory

+			tb_mdfn_wren	= 0;				// stop filling memory

 			//

 		end

 		//

 	endtask
 			

-	/*	

+

 	//

 	// write_memory_512

 	//

 	task write_memory_512;

 		//

+		input	[511:0] m;

+		input	[511:0] d;

+		input	[511:0] f;

 		input	[511:0] n;

+		input	[511:0] n_coeff;

+		reg	[511:0] m_shreg;

+		reg	[511:0] f_shreg;

+		reg	[511:0] d_shreg;

 		reg	[511:0] n_shreg;

+		reg	[511:0] n_coeff_shreg;

 		//

 		begin
 			//

-			tb_n_wren	= 1;	// start filling memories
-			n_shreg		= n;	// preload shift register

+			tb_mdfn_wren	= 1;			// start filling memories
+			m_shreg			= m;			// preload shift register

+			d_shreg			= d;			// preload shift register

+			f_shreg			= f;			// preload shift register

+			n_shreg			= n;			// preload shift register

+			n_coeff_shreg	= n_coeff;	// preload shift register

 			//
-			for (w=0; w<NUM_WORDS_512; w=w+1) begin				// write all words
-				tb_n_addr	= w[3:0];									// set address
-				tb_n_data	= n_shreg[31:0];							// set data
-				n_shreg		= {{32{1'bX}}, n_shreg[511:32]};		// update shift register
-				#10;															// wait for 1 clock tick
+			for (w=0; w<NUM_WORDS_512; w=w+1) begin							// write all words
+				tb_mdfn_addr		= w[3:0];											// set address
+				tb_m_data			= m_shreg[31:0];									// set data
+				tb_d_data			= d_shreg[31:0];									// set data
+				tb_f_data			= f_shreg[31:0];									// set data
+				tb_n_data			= n_shreg[31:0];									// set data
+				tb_n_coeff_data	= n_coeff_shreg[31:0];							// set data
+				m_shreg				= {{32{1'bX}}, m_shreg[511:32]};				// update shift register
+				d_shreg				= {{32{1'bX}}, d_shreg[511:32]};				// update shift register
+				f_shreg				= {{32{1'bX}}, f_shreg[511:32]};				// update shift register
+				n_shreg				= {{32{1'bX}}, n_shreg[511:32]};				// update shift register
+				n_coeff_shreg		= {{32{1'bX}}, n_coeff_shreg[511:32]};		// update shift register
+				#10;																			// wait for 1 clock tick
 			end
 			//
-			tb_n_addr	= {4{1'bX}};	// wipe addresses
-			tb_n_data	= {32{1'bX}};	// wipe data
-			tb_n_wren	= 0;				// stop filling memory

+			tb_mdfn_addr		= {4{1'bX}};	// wipe addresses
+			tb_m_data			= {32{1'bX}};	// wipe data
+			tb_d_data			= {32{1'bX}};	// wipe data
+			tb_f_data			= {32{1'bX}};	// wipe data
+			tb_n_data			= {32{1'bX}};	// wipe data
+			tb_n_coeff_data	= {32{1'bX}};	// wipe data
+			tb_mdfn_wren	= 0;				// stop filling memory

 			//

 		end

 		//

 	endtask
-	*/

+

 

 	//

 	// read_memory_384

@@ -392,30 +431,30 @@ module tb_exponentiator;
 		//

 	endtask
 

-	/*

+

 	//

 	// read_memory_512

 	//

 	task read_memory_512;

 		//

-		output	[511:0] f;

-		reg		[511:0] f_shreg;

+		output	[511:0] r;

+		reg		[511:0] r_shreg;

 		//

 		begin

 			//

 			for (w=0; w<NUM_WORDS_512; w=w+1) begin		// read result word-by-word
-				tb_f_addr	= w[3:0];							// set address
+				tb_r_addr	= w[3:0];							// set address
 				#10;													// wait for 1 clock tick
-				f_shreg = {tb_f_data, f_shreg[511:32]};	// store data word
+				r_shreg = {tb_r_data, r_shreg[511:32]};	// store data word
 			end

 			//

-			tb_f_addr = {4{1'bX}};								// wipe address

-			f = f_shreg;											// return

+			tb_r_addr = {4{1'bX}};								// wipe address

+			r = r_shreg;											// return

 			//

 		end

 		//

-	endtask

-	*/

+	endtask
+

 

 endmodule