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| author | Pavel V. Shatov (Meister) <meisterpaul1@yandex.ru> | 2017-07-01 02:05:02 +0300 |
|---|---|---|
| committer | Pavel V. Shatov (Meister) <meisterpaul1@yandex.ru> | 2017-07-01 02:05:02 +0300 |
| commit | 1fd8037d41be46d24b3610c89f781fe85def4317 (patch) | |
| tree | e407d6148e362bb3f24b46e634bd0ca01814b195 /src/rtl/util | |
| parent | 52675d5fa64a1157fe85e041914179309eb2ed9e (diff) | |
Finished modulus-dependent coefficient calculation module:
* fixed bug with latency compensation
* cleaned up Verilog source
* added 512-bit testbench
* works in simulator
* synthesizes without warnings
Changes:
* made latency of generic processing element configurable
Diffstat (limited to 'src/rtl/util')
0 files changed, 0 insertions, 0 deletions