From c54b20ea19ebbbd8fb646950c4608d89eb2b60e7 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joachim=20Stro=CC=88mbergson?= Date: Mon, 22 Jun 2015 15:15:04 +0200 Subject: Consolidated address settings, removed stale s logic mux control, removed extra lsw set. --- src/rtl/montprod.v | 14 ++++++-------- 1 file changed, 6 insertions(+), 8 deletions(-) (limited to 'src') diff --git a/src/rtl/montprod.v b/src/rtl/montprod.v index b03bf94..93ddacf 100644 --- a/src/rtl/montprod.v +++ b/src/rtl/montprod.v @@ -300,10 +300,10 @@ module montprod( if (montprod_ctrl_reg == CTRL_LOOP_ITER) - opa_addr_reg = length_m1; - - if (montprod_ctrl_reg == CTRL_LOOP_ITER) - s_mem_addr = length_m1; + begin + opa_addr_reg = length_m1; + s_mem_addr = length_m1; + end if (montprod_ctrl_reg == CTRL_EMIT_S) tmp_result_we = 1'b1; @@ -470,7 +470,7 @@ module montprod( begin ready_new = 1'b0; ready_we = 1'b1; - first_iteration_new = 1'b0; + first_iteration_new = 1'b1; first_iteration_we = 1'b1; reset_word_index_lsw = 1'b1; montprod_ctrl_new = CTRL_INIT_S; @@ -480,10 +480,9 @@ module montprod( CTRL_INIT_S: begin - s_mux_new = SMUX_0; // write 0 - if (word_index_reg == 8'h0) begin + loop_ctr_set = 1'b1; montprod_ctrl_new = CTRL_WAIT; montprod_ctrl_we = 1'b1; end @@ -501,7 +500,6 @@ module montprod( CTRL_LOOP_ITER: begin b_bit_index_we = 1'b1; - reset_word_index_lsw = 1'b1; montprod_ctrl_new = CTRL_LOOP_BQ; montprod_ctrl_we = 1'b1; end -- cgit v1.2.3