From a315223f98fa6f1fdea2b1080c5f3e33352ebb13 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joachim=20Stro=CC=88mbergson?= Date: Mon, 27 Apr 2015 11:17:08 +0200 Subject: Updating modexp core to v 0.50. This version contains a working core that can perform sign and verify with big keys/values. The core builds ok in Altera and Xilinx FPGA tools. This commit also includes a new testgenerator capable of generating testbench for modexp with autgenerated test data of different lengths. The README has been updated with status and implementation results in for different FPGA devices. --- src/tb/tb_residue.v | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'src/tb/tb_residue.v') diff --git a/src/tb/tb_residue.v b/src/tb/tb_residue.v index 4978bf9..4bb2922 100644 --- a/src/tb/tb_residue.v +++ b/src/tb/tb_residue.v @@ -203,7 +203,7 @@ task reset_dut(); begin $display("*** Toggle reset."); tb_reset_n = 0; - #(4 * CLK_HALF_PERIOD); + #(2 * CLK_PERIOD); tb_reset_n = 1; end endtask // reset_dut @@ -242,9 +242,9 @@ task wait_ready(); integer i; for (i=0; i<100000000; i=i+1) if (tb_ready == 0) - #(2 * CLK_HALF_PERIOD); + #(CLK_PERIOD); else if (tb_ready === 1) - i = 100000000000000000000; + i = 1000000000; end if (tb_ready == 0) begin @@ -263,7 +263,7 @@ task signal_calculate(); begin $display("*** signal_calculate"); tb_calculate = 1; - #(2 * CLK_HALF_PERIOD); + #(CLK_PERIOD); tb_calculate = 0; end endtask // signal_calculate -- cgit v1.2.3