From 5775903b6e158624799889fffa70555437df08ce Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Joachim=20Stro=CC=88mbergson?= <joachim@secworks.se>
Date: Mon, 15 Jun 2015 18:01:33 +0200
Subject: cleanup of s mem write control.

---
 src/rtl/montprod.v | 13 +++++++------
 1 file changed, 7 insertions(+), 6 deletions(-)

(limited to 'src/rtl/montprod.v')

diff --git a/src/rtl/montprod.v b/src/rtl/montprod.v
index 1b9346f..9b112f4 100644
--- a/src/rtl/montprod.v
+++ b/src/rtl/montprod.v
@@ -247,6 +247,7 @@ module montprod(
           add_carry_in_sm_reg <= add_carry_in_sm_new;
 
           B_bit_index_reg <= B_bit_index;
+
           q_reg <= q;
           b_reg <= b;
 
@@ -404,28 +405,28 @@ module montprod(
   always @*
     begin : s_writer
       shr_carry_in_new    = 1'b0;
-      s_mux_new        = SMUX_0;
+      s_mux_new     = SMUX_0;
       s_mem_we_new  = 1'b0;
 
       case (montprod_ctrl_reg)
         CTRL_INIT_S:
           begin
-            s_mem_we_new = 1'b1;
             s_mux_new    = SMUX_0; // write 0
+            s_mem_we_new = 1'b1;
           end
 
         CTRL_L_CALC_SM:
           begin
             //s = (s + q*M + b*A) >>> 1;, if(q==1) S+= M. Takes (1..length) cycles.
-            s_mem_we_new     = q_reg;
-            s_mux_new        = SMUX_ADD_SM;
+            s_mux_new    = SMUX_ADD_SM;
+            s_mem_we_new = q_reg;
           end
 
         CTRL_L_CALC_SA:
           begin
             //s = (s + q*M + b*A) >>> 1;, if(b==1) S+= A. Takes (1..length) cycles.
-            s_mem_we_new     = b_reg;
-            s_mux_new        = SMUX_ADD_SA;
+            s_mux_new    = SMUX_ADD_SA;
+            s_mem_we_new = b_reg;
           end
 
         CTRL_L_CALC_SDIV2:
-- 
cgit v1.2.3