From 79fd97bbf808daea40bdc502eff015929d993610 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Joachim=20Stro=CC=88mbergson?= <joachim@secworks.se>
Date: Fri, 26 Jun 2015 09:08:43 +0200
Subject: Added test register for cycle trace. Moved index counter update under
 if-else to remove spurious s_mem read.

---
 src/rtl/montprod.v | 25 +++++++++++++++++--------
 1 file changed, 17 insertions(+), 8 deletions(-)

diff --git a/src/rtl/montprod.v b/src/rtl/montprod.v
index 279f5aa..12260ac 100644
--- a/src/rtl/montprod.v
+++ b/src/rtl/montprod.v
@@ -138,6 +138,9 @@ module montprod #(parameter OPW = 32, parameter ADW = 8)
   reg                  first_iteration_new;
   reg                  first_iteration_we;
 
+  reg                  test_reg;
+  reg                  test_new;
+
 
   //----------------------------------------------------------------
   // Wires.
@@ -170,7 +173,6 @@ module montprod #(parameter OPW = 32, parameter ADW = 8)
   // Temporary debug wires.
   reg [1 : 0] state_trace;
   reg [1 : 0] mux_trace;
-  reg         s_mem_we;
 
 
   //----------------------------------------------------------------
@@ -196,7 +198,7 @@ module montprod #(parameter OPW = 32, parameter ADW = 8)
                                              .clk(clk),
                                              .read_addr(s_mem_read_addr),
                                              .read_data(s_mem_read_data),
-                                             .wr(s_mem_we_reg | s_mem_we),
+                                             .wr(s_mem_we_reg),
                                              .write_addr(s_mem_write_addr),
                                              .write_data(s_mem_write_data)
                                             );
@@ -237,6 +239,7 @@ module montprod #(parameter OPW = 32, parameter ADW = 8)
     begin : reg_update
       if (!reset_n)
         begin
+          test_reg            <= 1'b1;
           ready_reg           <= 1'b1;
           loop_ctr_reg        <= 13'h0;
           word_index_reg      <= {ADW{1'b0}};
@@ -255,6 +258,8 @@ module montprod #(parameter OPW = 32, parameter ADW = 8)
         end
       else
         begin
+          test_reg            <= test_new;
+
           s_mem_read_addr_reg <= s_mem_read_addr;
           s_mem_we_reg        <= s_mem_we_new;
           s_mux_reg           <= s_mux_new;
@@ -311,10 +316,11 @@ module montprod #(parameter OPW = 32, parameter ADW = 8)
       s_mem_write_addr      = s_mem_read_addr_reg;
       s_mem_write_data      = {OPW{1'b0}};
       s_mem_we_new          = 1'b0;
-      s_mem_we              = 1'b0;
       state_trace           = 0;
       mux_trace             = 0;
       tmp_s_mem_write_data  = {OPW{1'b0}};
+      test_new              = 1'b0;
+
 
       case (montprod_ctrl_reg)
         CTRL_LOOP_ITER:
@@ -326,7 +332,8 @@ module montprod #(parameter OPW = 32, parameter ADW = 8)
           begin
             //s = (s + q*M + b*A) >>> 1;, if(b==1) S+= A. Takes (1..length) cycles.
             s_mem_we_new = b_reg | q_reg | first_iteration_reg;
-            state_trace = 1;
+            state_trace  = 1;
+            test_new     = 1'b1;
           end
 
         CTRL_CALC_SDIV2:
@@ -345,7 +352,6 @@ module montprod #(parameter OPW = 32, parameter ADW = 8)
         SMUX_ADD:
           begin
             mux_trace = 1;
-            s_mem_we = b_reg | q_reg | first_iteration_reg;
 
             if (first_iteration_reg)
               muxed_s_mem_read_data = {OPW{1'b0}};
@@ -374,7 +380,6 @@ module montprod #(parameter OPW = 32, parameter ADW = 8)
 
         SMUX_SHR:
           begin
-            s_mem_we         = 1'b1;
             shr_data_in      = s_mem_read_data;
             s_mem_write_data = shr_data_out;
             shr_carry_in_new = shr_carry_out;
@@ -533,7 +538,6 @@ module montprod #(parameter OPW = 32, parameter ADW = 8)
         CTRL_CALC_ADD:
           begin
             s_mux_new      = SMUX_ADD;
-            dec_word_index = 1'b1;
 
             if (word_index_reg == 0)
               begin
@@ -541,6 +545,10 @@ module montprod #(parameter OPW = 32, parameter ADW = 8)
                 montprod_ctrl_new    = CTRL_STALLPIPE_ADD;
                 montprod_ctrl_we     = 1'b1;
               end
+            else
+              begin
+                dec_word_index = 1'b1;
+              end
           end
 
         CTRL_STALLPIPE_ADD:
@@ -555,13 +563,14 @@ module montprod #(parameter OPW = 32, parameter ADW = 8)
         CTRL_CALC_SDIV2:
           begin
             s_mux_new      = SMUX_SHR;
-            inc_word_index = 1'b1;
 
             if (word_index_reg == length_m1)
               begin
                 montprod_ctrl_new = CTRL_STALLPIPE_SDIV2;
                 montprod_ctrl_we  = 1'b1;
               end
+            else
+              inc_word_index = 1'b1;
           end
 
         CTRL_STALLPIPE_SDIV2:
-- 
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